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Design and build compilers, emulators, profilers and debuggers for error-corrected quantum systems. Implement QEC codes and runtimes, write maintainable code, collaborate with scientists and engineers, and deliver components of an LLVM MLIR-based compiler and runtime.

Lead design and implementation of a LLVM/MLIR-based compiler toolchain for error-corrected quantum computing. Build compilers, emulators, profilers, and debuggers; implement optimizations and IR transformations; own substantial parts of the software stack; mentor engineers; collaborate with hardware and science teams to integrate error-correcting codes and runtimes.

Lead FPGA integration for Riverlane's Deltaflow hardware: write RTL, implement and verify FPGA designs, benchmark latency, support on-site system deployments, debug with customers, and feed product improvements back to engineering and product teams.

Own end-to-end functional verification for block- and system-level designs. Define verification plans and strategies, build scalable SystemVerilog testbenches (UVM/OVM) with checkers, reference models, and SVA. Implement directed, random and self-testing, track regressions, coverage metrics and bugs, and debug across RTL, simulation and hardware. Collaborate with designers and architects to ensure high quality and reliability.

Lead integration and deployment of low-latency, high-throughput compiler software for Riverlane's DeltaFlow hardware. Work with customers on technical pre-sales, on-site system integration, benchmarking, debugging, and feedback to product teams. Write Python/C++ (or Rust), adapt low-level code to quantum control systems, and collaborate with QA and application teams to validate and improve systems.