Top Tech Jobs & Startup Jobs

Lead development of Deltakit, turning QEC research into robust open-source software. Drive design, delivery, performance and scalability, mentor engineers, collaborate across teams, engage the research community, and run workshops to support adoption and shape technical direction.

Lead verification across block, subsystem and multi-FPGA system designs. Define and execute verification strategy, build scalable UVM testbenches, drive coverage/risk-based verification, debug RTL/simulation/hardware, and establish verification best practices.

Lead design and implementation of a LLVM/MLIR-based compiler toolchain for error-corrected quantum computing. Build compilers, emulators, profilers, and debuggers; implement optimizations and IR transformations; own substantial parts of the software stack; mentor engineers; collaborate with hardware and science teams to integrate error-correcting codes and runtimes.

Design and optimize RTL for multi-FPGA and ASIC systems to achieve low latency and high throughput. Develop deeply pipelined high‑clock modules, test and debug complex systems, review specifications and mentor junior engineers, and translate product requirements into technical specifications.

Lead the strategy and roadmap for Deltakit, an open-source QEC SDK. Engage users and partners, prioritise features, align cross-functional teams, support launches, drive developer adoption and community growth, and ensure strong documentation and onboarding.

Lead and set the direction for Riverlane's open-source SDK (Deltakit), driving teams that build simulators, analysis tools, visualizers and core components. Prioritise community-facing components, collaborate with product and internal developers, engage the global developer community, and amplify internal engineering efforts to produce widely accessible software.

Lead FPGA integration for Riverlane's Deltaflow hardware: write RTL, implement and verify FPGA designs, benchmark latency, support on-site system deployments, debug with customers, and feed product improvements back to engineering and product teams.

Own end-to-end functional verification for block- and system-level designs. Define verification plans and strategies, build scalable SystemVerilog testbenches (UVM/OVM) with checkers, reference models, and SVA. Implement directed, random and self-testing, track regressions, coverage metrics and bugs, and debug across RTL, simulation and hardware. Collaborate with designers and architects to ensure high quality and reliability.

Lead integration and deployment of low-latency, high-throughput compiler software for Riverlane's DeltaFlow hardware. Work with customers on technical pre-sales, on-site system integration, benchmarking, debugging, and feedback to product teams. Write Python/C++ (or Rust), adapt low-level code to quantum control systems, and collaborate with QA and application teams to validate and improve systems.

Lead Deltaflow product strategy and roadmap for quantum error correction. Engage customers and partners to gather insight, translate technical research into usable products, prioritize features, align cross-functional teams, support go-to-market and launches, and produce product collateral. Balance long-term ambition with technical and commercial feasibility while staying close to delivery and adapting to new insights.