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Lead standardization and definition of system-level functional safety architectures for PMIC/power ICs. Mentor FuSa managers, align requirements with MCU/SoC teams, define reusable FuSa libraries and tool flows, interface with assessors and customers, advise design and validation, and drive tool-based and AI-assisted FuSa workflows.

Lead development of ATE test programs, support qualification/characterization, mentor junior engineers, implement test processes and hardware/software solutions, support production yield and equipment maintenance, and coordinate cross-functional and third-party teams for analog power product testing.

Design and develop high-voltage GaN products, coordinate engineering lots through wafer fab, packaging and testing, generate test and qualification protocols, analyze on-wafer and in-package results, drive root-cause failure analysis, manage qualification campaigns and project schedules, and communicate status, risks, and results to internal and external stakeholders.

Lead standardization of functional safety (FuSa) definitions for PMIC/power ICs, advise system/chip architects, create reusable FuSa libraries, define requirements, interface with assessors and customers, drive tool-based FuSa workflows, mentor FuSa engineers, and validate implementations while minimizing cost and design complexity.

Own and drive regional solution strategy for SEA and ANZ, define system architectures and solution specs, lead proposal creation with TAAs, coordinate solution development with product groups and partners, execute GTM and channel enablement, perform competitive analysis and customer feedback synthesis, and measure solution impact using CRM and reporting tools to refine strategy and portfolio.

Lead standardization and definition of functional safety (FuSa) architectures for PMIC/power IC products. Define system-level FuSa requirements, create reusable FuSa library, align with MCU/SoC teams, interface with safety assessors, guide product teams on implementations, review simulations and validations, drive tool-based FuSa workflows, mentor FuSa engineers, and engage with customers and stakeholders. Travel for customer/internal meetings required.

The Staff Hardware Engineer will support NFC Point-Of-Sale and IoT domains, design PCBs, lead customer projects, and conduct RF measurements and EMC tests.

Design and architect Verilog RTL for mixed-signal memory buffer ASICs (DDR5/DDR6+), lead digital implementation (synthesis, STA, P&R hand-off), verification (formal, lint, CDC), DFT and gate-level debug, produce documentation, and mentor junior engineers.

The role involves executing RTL-to-GDSII flows, performing timing analysis, and verifying designs while collaborating with cross-functional teams on complex designs.

Design optimized digital blocks, develop TCL scripts, ensure compliance with specifications, support DFT strategy, conduct verification planning, and produce documentation.