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The Staff DevOps Engineer will design cloud-native environments, optimize CI/CD processes, mentor team members, and collaborate with software development teams.

Design and verify CMOS analog blocks for ASICs, lead subsystems, guide layouts, produce documentation, drive silicon debugging, and mentor junior team members.

Lead the development of DDR5 and DDR6 PHY solutions, managing a team focused on high-speed memory interfaces, overseeing design and implementation, ensuring compliance with standards, and fostering technical excellence.

As a Staff DevOps Engineer, you'll architect cloud-native environments, optimize CI/CD processes, mentor team members, and enhance infrastructure excellence.

Design and implement digital modules for automotive SoCs: microarchitecture, RTL coding, synthesis, CDC, lint, STA, scan/DFT, UPF/power intent, verification support, and cross-team integration to complete product releases.

The Principal Digital Verification Engineer is responsible for verifying DDR5 Data Buffers, developing verification plans, creating reusable test environments, and leading a team in memory interface product verification for optimal performance and quality.

Lead verification of power efficient IPs, manage the verification team, deliver quality, develop test plans, and support post silicon debug.

The Staff DevOps Engineer will architect cloud-native environments, optimize CI/CD pipelines, build infrastructure, and mentor team members to drive automation and project management.

The Test Engineer develops test programs and hardware for Memory Interface Devices, collaborates with functionality teams, and implements best testing practices.

Define SoC/MCU architecture and specifications, collaborate with teams to refine architecture, and support post-silicon debug and validation.