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Senior-level program manager and chief of staff supporting the CVP of Operations. Own and drive high-priority cross-functional programs from kickoff through execution, establish operating cadences, align teams on priorities, prepare leadership materials, integrate sales & operations, headcount and infrastructure planning, surface risks, and remove execution blockers to ensure organizational KPIs and milestones are met.

The role involves designing and optimizing performance-critical kernels for AI hardware, debugging low-level issues, and collaborating with cross-functional teams.

The Sr. Engineer will work on CPU design, focusing on RTL implementation, collaborating with micro-architects, and optimizing performance, power, and area.

Own Tenstorrent's developer platform including firmware, system software, packaging, updates, and a unified CLI. Define roadmap, prioritize engineering work, partner with DevRel and customers, ship iterative improvements, and measure success via developer NPS and CLI adoption.

Build and operate AI inference deployments, write production code, debug full inference stack, collaborate with customers and engineering, and drive performance/observability improvements using Kubernetes, Helm, and LLM serving tools.

Design, implement, and optimize low-level compute kernels for parallel ML workloads. Write high-performance C/C++ code, tune instruction-level latency, memory, and bandwidth, profile and debug a low-level software stack, and collaborate with ML and hardware engineers to integrate optimizations into production ML pipelines.

As a Staff Engineer, you will own verification for CPU core features, develop functional models, and collaborate with cross-functional teams to enhance design quality.

As a Senior Engineer, develop low-level firmware for Ethernet components, drive silicon bring-up, and optimize networking hardware. Collaborate closely with silicon architects and debug hardware-software interactions.

Develop, deploy, and own RTL-to-GDSII physical design methodology and CAD flows for IP delivery. Automate PPA exploration, document flows, partner with design teams and EDA vendors, qualify new nodes/PDKs and EDA releases, and apply ML/LLMs where they improve flow optimization and scalability.

Design and validate high-bandwidth interconnects for AI clusters across copper and optical media. Define architectures, perform link and channel budget analysis, lead qualification and reliability testing, develop validation plans for transceivers and cables up to 1.6T, and coordinate with suppliers and manufacturing.