Top Tech Jobs & Startup Jobs

The role involves designing and optimizing performance-critical kernels for AI hardware, debugging low-level issues, and collaborating with cross-functional teams.

The Sr. Engineer will work on CPU design, focusing on RTL implementation, collaborating with micro-architects, and optimizing performance, power, and area.

Lead and scale accounting operations (AP, AR, payroll accounting, fixed assets, accruals, reconciliations, and close). Improve close cycle, strengthen internal controls, drive ERP/process automation, build a high-performing global team, and manage auditors, consultants, and outsourced partners to support rapid growth and public-company readiness.

As a SOC Emulation Engineer, you'll support hardware emulation infrastructure, integrating hardware transactors and developing Python-based test frameworks while providing technical support across chip projects.

Own Tenstorrent's developer platform including firmware, system software, packaging, updates, and a unified CLI. Define roadmap, prioritize engineering work, partner with DevRel and customers, ship iterative improvements, and measure success via developer NPS and CLI adoption.

Build and operate AI inference deployments, write production code, debug full inference stack, collaborate with customers and engineering, and drive performance/observability improvements using Kubernetes, Helm, and LLM serving tools.

Design, implement, and optimize low-level compute kernels for parallel ML workloads. Write high-performance C/C++ code, tune instruction-level latency, memory, and bandwidth, profile and debug a low-level software stack, and collaborate with ML and hardware engineers to integrate optimizations into production ML pipelines.

As a Staff Engineer, you will own verification for CPU core features, develop functional models, and collaborate with cross-functional teams to enhance design quality.

As a Senior Engineer, develop low-level firmware for Ethernet components, drive silicon bring-up, and optimize networking hardware. Collaborate closely with silicon architects and debug hardware-software interactions.

Develop, deploy, and own RTL-to-GDSII physical design methodology and CAD flows for IP delivery. Automate PPA exploration, document flows, partner with design teams and EDA vendors, qualify new nodes/PDKs and EDA releases, and apply ML/LLMs where they improve flow optimization and scalability.