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As a Senior Chiplet Physical Design Engineer, you'll design and integrate chiplets into a System-in-Package, focusing on synthesis and place-and-route, while collaborating with global teams.

The Performance Architect will work on high-performance systems with expertise in software and hardware, focusing on AI and HPC solutions.

Develop and optimize distributed software systems for AI and HPC clusters, focusing on inter-node communication and scalable architectures.

Design, implement, and maintain TT-Fabric, a low-level high-performance networking library for large-scale AI clusters. Build scalable communication protocols, optimize synchronization and data movement for thousands of processors, integrate APIs with AI and hardware teams, and help define the distributed systems architecture to maximize hardware performance.

Lead CPU core-level testbench development and verification for high-performance out-of-order RISC-V CPUs, involving hands-on infrastructure development and debugging using AI methodologies.

Lead customer engagements for RISC-V CPU server and machine learning processor projects, coordinating with engineering teams and managing technical program requirements.

Lead post-silicon power characterization and correlation for semiconductor products, develop measurement strategies, and improve power architectures to meet specifications.

The role involves defining and implementing RTL for high-performance RISC-V CPUs, collaborating with various teams to ensure design meets functional, timing, and power goals while using innovative optimization techniques.

Senior-level program manager and chief of staff supporting the CVP of Operations. Own and drive high-priority cross-functional programs from kickoff through execution, establish operating cadences, align teams on priorities, prepare leadership materials, integrate sales & operations, headcount and infrastructure planning, surface risks, and remove execution blockers to ensure organizational KPIs and milestones are met.

The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.