Top Tech Jobs & Startup Jobs

Own Tenstorrent’s cloud sales segment from customer discovery through production deployment and revenue growth. Build pipeline, account strategies, forecasts, and a repeatable go-to-market motion for neoclouds, inference providers, model-as-a-service platforms, edge networks, and capacity aggregators. Identify differentiated AI workloads, lead technical evaluations and commercial negotiations, and partner with Product, Engineering, Field Applications, Marketing, and sales teams to drive adoption and strategic customer outcomes.

The Risc-V Architect will analyze AI workloads, design custom RISC-V cores, and lead the architecture efforts at Tenstorrent, improving CPU performance.

Physical Design Engineers at Tenstorrent are responsible for implementing high-performance AI SoC designs, overseeing the complete implementation flow from synthesis to tapeout and collaborating with cross-functional teams to ensure all design aspects are met.

As a Verification Engineer, you'll verify digital IP and SoC logic, develop components for verification infrastructure, create test plans, and guide junior engineers in a collaborative environment.

Design, implement, and optimize performance-critical GPU-style kernels (e.g., matmul, attention) and host-side orchestration. Identify bottlenecks, deliver measurable throughput improvements, create micro-benchmarks, regression tests, and tooling, and collaborate with compiler, runtime, ML, and hardware teams to integrate kernels into production.

Develop and optimize low-level infrastructure software that interfaces with Tenstorrent hardware. Build libraries and APIs for inter-node communication and synchronization, improve performance and scalability in distributed environments, support hardware bring-up, testing, deployment, and integrate components with runtimes and programming models.

As a RISC-V AI/HPC Software Engineer at Tenstorrent, you will integrate and optimize AI and HPC software stacks with RISC-V CPUs, collaborating across teams to design and implement performance-focused architectures and tools.

Shape and evaluate next-generation high-performance RISC-V CPUs using performance modeling and simulation. Build and run architectural models (Gem5/SST/SimpleScalar), analyze pipelines, caches, branch prediction, and memory hierarchies, implement modeling and analysis tools in C++/Python, and collaborate with CPU architects to optimize AI/HPC workload performance. Hybrid role based in Santa Clara or Austin.

Design and implement chip-level DFT strategies for high-speed CPU cores and multi-chiplet SiP. Implement and verify scan chains, memory BIST, and JTAG. Partner with RTL, physical design, and verification teams. Script and automate DFT flows using EDA tools (ATPG, fault coverage) and support SoC-level silicon debug, formal verification, and DFT signoff.

Leads the strategy, architecture, implementation, and evolution of Finance Systems. Owns ERP and financial systems roadmaps, finance process transformation, integrations, data architecture, automation, AI applications, controls, and cross-functional technology programs. Builds a scalable, data-driven Finance technology organization supporting global growth, accounting, tax, treasury, supply chain, manufacturing, reporting, and planning.