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As a Chip Design Lead at Tenstorrent, you will oversee the development of SoC programs from architecture to deployment, ensuring collaboration across teams and managing chip lifecycle processes.

The Sr. Software Engineer will develop AI compiler technologies, optimizing models for Tenstorrent hardware, and engage in collaborative problem-solving with a focus on open-source contributions.

As a Verification Engineer, you'll verify digital IP and SoC logic, develop components for verification infrastructure, create test plans, and guide junior engineers in a collaborative environment.

Design, implement, and optimize performance-critical GPU-style kernels (e.g., matmul, attention) and host-side orchestration. Identify bottlenecks, deliver measurable throughput improvements, create micro-benchmarks, regression tests, and tooling, and collaborate with compiler, runtime, ML, and hardware teams to integrate kernels into production.

Develop and optimize low-level infrastructure software that interfaces with Tenstorrent hardware. Build libraries and APIs for inter-node communication and synchronization, improve performance and scalability in distributed environments, support hardware bring-up, testing, deployment, and integrate components with runtimes and programming models.

Lead technical sales efforts in Singapore for AI and compute hardware/IP. Own client relationships, identify new business, translate technical requirements into value propositions, collaborate cross-functionally, and meet revenue targets while supporting long-term customer success.

As an AI Processor IP Product Engineer, you'll facilitate customer integration of AI processors into SoCs, ensuring performance and market readiness. Responsibilities include technical support and debugging complex systems.

The engineer will join a CPU design team focusing on performance analysis, verification, and collaboration with architects to deliver efficient CPU designs using RISC-V ISA.

Partner with the C-suite to execute M&A, lead financial and business modeling for deals and fundraising, build/manage strategic partnerships across AI/semiconductor/data center ecosystems, prepare board-level strategy materials, and support government relations and stakeholder engagement.

Design and implement chip-level DFT strategies for high-speed CPU cores and multi-chiplet SiP. Implement and verify scan chains, memory BIST, and JTAG. Partner with RTL, physical design, and verification teams. Script and automate DFT flows using EDA tools (ATPG, fault coverage) and support SoC-level silicon debug, formal verification, and DFT signoff.