Top Tech Jobs & Startup Jobs

The Corporate Controller will lead a global accounting organization, ensuring predictable monthly, quarterly, and annual closes, accurate financial reporting, strong controls, documented accounting policies, audit readiness, and risk management. The role partners with Commercial, Legal, Tax, Treasury, Operations, and Strategic Finance, while scaling teams, systems, and processes through rapid growth. Responsibilities include accounting policy across revenue, inventory, leases, equity, debt, and foreign currency, plus replacing manual work with ERP, automation, data, and AI-enabled tools.

Own global OSAT partnerships and backend semiconductor manufacturing execution from wafer-out through final shipment. Manage supplier relationships, negotiations, engineering builds, qualification, yield ramps, capacity, materials, production schedules, substrates, logistics, quality, and supply risks. Establish KPIs, data processes, and analytics across Taiwan-based OSAT partners supporting advanced packaging, HBM, and AI compute products.

Supports corporate development and strategic deal processes, including partnerships, business development, strategic sales, pipeline and CRM management, research, briefing materials, diligence, data-room organization, and executive communications. The role coordinates multiple workstreams and supports senior leadership throughout commercial transactions in the AI hardware, semiconductor, and data center ecosystems.

Leads analysis, modeling, structuring, negotiation, and execution of strategic partnerships and commercial transactions. Builds business cases, develops relationships across the AI, semiconductor, and data center ecosystems, manages deal workstreams, and presents strategy recommendations to senior executives and external partners.

Defines and leads physical design methodology, automation, and signoff infrastructure for high-performance CPU cores across advanced process nodes. Owns RTL-to-GDS flows spanning synthesis, floorplanning, power planning, place and route, timing, signal integrity, EM/IR, extraction, and physical verification. Drives scalable automation, quality metrics, dashboards, and AI/ML-enabled tooling while partnering across architecture, RTL, CAD, DFT, data, program, and EDA teams.

Owns end-to-end monthly payroll operations across Serbia, Poland, and additional EMEA countries. Responsibilities include coordinating with ADP Celergo and local providers, validating employee data, managing payroll calendars, reconciliations, funding, payments, statutory requirements, reporting, audits, and issue resolution. The role also improves payroll controls, documentation, workflows, data quality, and automation while supporting new entity launches and payroll expansions.

Leads end-to-end design verification for CPU, AI accelerator, and chiplet platforms. Develops SV-UVM, C/DPI, and Cocotb simulation environments; owns test plans, coverage, regressions, failure triage, and sign-off. Collaborates with architecture, design, software, and post-silicon teams, supports emulation and multi-chip verification, and mentors junior engineers. Uses AI-assisted tools to improve verification workflows and scalability.

Lead cross-functional technical programs for AI hardware and systems from concept through production. Coordinate hardware, software, firmware, validation, manufacturing, and supplier teams; manage schedules, risks, dependencies, and stakeholder communications; align teams around shared goals; and deliver complex products on schedule.

Lead the Bangalore CPU Core Design Verification team for high-performance, out-of-order RISC-V CPUs. Own verification strategy, methodology, coverage, infrastructure, tapeout readiness, and cross-site execution. Hire, mentor, and manage verification engineers while remaining technically engaged in debugging, reviews, regressions, and closure of critical issues. Partner with Design, Emulation, and Post-Silicon teams across global locations and champion AI-assisted verification workflows.

Verify RISC-V CPU front-end units, including instruction fetch, branch prediction, caches, TLBs, and fetch control structures. Build UVM testbenches, constrained-random and directed stimulus, checkers, transactors, predictors, scoreboards, and C++ reference models. Execute verification plans, track functional and code coverage, and resolve microarchitectural edge cases with RTL, performance modeling, and software teams using simulation and emulation workflows.