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As a Software Engineer specializing in AI Compilers, you will design, develop, and optimize compilers for advanced semiconductor products, working collaboratively with engineers to enhance performance of machine learning applications and integrate software into leading frameworks.

The Staff Design Verification Engineer will create verification plans and develop DV environments primarily using System Verilog and UVM methodologies. Responsibilities include executing test plans, performing functional verification at the RTL level, and developing Universal Verification Components. Candidates must have a Bachelor's or Master's degree in relevant fields and experience in DV and verification methodologies.

As a Gate-Level Simulation Engineer, you'll develop methodologies and conduct simulations to verify the performance and functionality of high-performance CPUs. The role involves collaboration with design teams, generating test plans, analyzing results, automating workflows, and maintaining simulation environments.