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Support and scale recruiting operations by managing interview scheduling, candidate communications, and hiring documentation; administer and optimize applicant tracking systems, workflows, templates, and reporting; partner with recruiters and hiring managers to meet service levels; support recruiting tool implementations, automation initiatives, and process improvements; maintain recruiting documentation and operational reporting to improve visibility and decision-making.

As a Senior Engineer in System-Level Design Verification, you will validate AI silicon's performance, ensuring system connectivity and functionality across large compute platforms, while collaborating with hardware and software teams to achieve silicon targets.

Design and architect chiplets for automotive SoC, focusing on performance and safety requirements while collaborating across engineering teams.

Lead architecture, development, customization, and technical oversight for core business applications and integrations (ERP, CRM, SaaS). Drive middleware and iPaaS strategy, design secure scalable APIs and microservices, manage system performance, upgrades, and risk mitigation, and provide hands-on technical leadership across integrations and cloud platforms.

The Staff Technical Program Manager will lead semiconductor physical design projects, managing complex schedules and facilitating communication between teams and clients within AI/ML and CPU initiatives.

Define and own chiplet-based compute platform architectures for high-performance RISC-V CPUs in SiP solutions. Lead design of PCIe, die-to-die connectivity, coherent fabrics, system management, and confidential computing subsystems. Collaborate with architecture, hardware, software, and external IP partners to deliver production-ready chiplet architectures and drive cross-functional execution.

As Director of Customer Engineering, manage technical customer relationships, translate needs into engineering specifications, and enhance collaboration between customer teams and internal engineering.

Design and optimize high-performance SoC and IP architectures for AI workloads, focusing on RTL implementation, power, performance, and area optimization.

Design, develop, and optimize GCC and LLVM compilers for RISC-V and AI architectures, collaborating across hardware and software teams to enhance performance.

Design and simulate high-speed interconnects, collaborate with teams on specifications, troubleshoot issues, and support post-silicon bring-up and validation.