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Design, develop, and optimize GCC and LLVM compilers for RISC-V and AI architectures, collaborating across hardware and software teams to enhance performance.

Design and simulate high-speed interconnects, collaborate with teams on specifications, troubleshoot issues, and support post-silicon bring-up and validation.

Build and operate engineering infrastructure for AI hardware and software: improve observability, automate workflows, maintain CI/CD pipelines, diagnose complex cross-layer issues across hardware, firmware, and distributed systems, and drive reliability and productivity improvements.

The engineer will focus on pre-silicon verification of DFD logic in AI SoCs, developing environments, analyzing coverage gaps, and automating testing flows.

Design Verification Engineer responsible for verifying Tensix IP, building reusable SystemVerilog/Python testbenches and DV infrastructure, developing constrained-random and directed tests, closing coverage, debugging RTL/testbench/workload issues, and integrating CI/CD, simulation/emulation, and containerized regression systems. Collaborates with design, firmware, compiler, and architecture teams.

Design and specify next-generation CPU networking for datacenter and automotive/robotics targets. Work at the intersection of NoC, performance modeling, and RTL to guide architecture, collaborate with hardware, software, and systems teams, and contribute to datacenter networking and early-stage automotive/robotics networking scoping and specifications.

As a Staff Machine Learning Engineer, you will optimize AI models for custom devices, experiment with state-of-the-art architectures, and collaborate to solve complex problems in real-world applications.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.

Develop and optimize the ML training framework in high-performance C++, implement new ops and layers, debug and tune model performance on Tenstorrent chips, collaborate with compiler and kernel teams, and support integration and productionization of real-world models.