Top Tech Jobs & Startup Jobs

Designs and optimizes power distribution systems for high-performance AI accelerator cards. Responsibilities include component selection, simulation, schematic and layout guidance, VRM bring-up, validation, debugging, power integrity and PDN optimization, thermal and EMI/EMC considerations, and production readiness. The role collaborates with hardware, firmware, software, thermal, mechanical, and validation teams throughout the hardware development lifecycle.

Designs high-performance AI/ML chips from synthesis through tapeout. Responsibilities include floorplanning, clocking, I/O planning, place-and-route, timing closure, power and area optimization, and EM/IR analysis. The engineer collaborates across front-end and physical design teams, develops ASIC implementation flows, and applies low-power techniques such as power gating, multi-Vt, and voltage scaling. The hybrid role is based in Austin, Fort Collins, or Santa Clara.

Architect and design liquid cooling infrastructure for large-scale AI training and inference clusters. Develop chassis-, rack-, and cluster-level solutions involving CDUs, telemetry, controls, leak detection, pressure testing, fluid compatibility, redundancy, and resilient operating strategies. Partner with systems, mechanical, software, facility, and cross-functional engineering teams to deliver reliable datacenter architectures for internal and external customers.

Drive static timing analysis and timing convergence for multi-million-gate semiconductor designs on advanced process nodes. Develop constraints, timing models, closure strategies, ECOs, and automation flows; analyze violations across process corners and coordinate with Design and DFT teams through final signoff and tapeout.

Analyze and optimize multicore CPU cluster performance across caches, coherence, interconnects, memory bandwidth, latency, and scalability. Build performance models and simulations using Gem5 or equivalent, study real workloads, identify bottlenecks, lead architectural tradeoff studies, and translate performance insights into design decisions through collaboration with CPU, RTL, compiler, software, and system architecture teams.

Verify high-performance RISC-V CPU cores by developing test plans, UVM testbenches, constrained-random tests, assertions, and functional coverage. Debug RTL and simulation failures using waveform and simulation tools, identify root causes, and drive issues to closure. Collaborate with CPU architects, RTL designers, software engineers, and verification teams across architecture, microarchitecture, and the design lifecycle.

Plan end-to-end silicon supply from wafer starts through assembly and test across foundry and OSAT partners. Translate demand forecasts into wafer requirements, monitor production, capacity, inventory, WIP, cycle times, and material readiness, and identify supply risks. Coordinate recovery actions with suppliers and cross-functional teams while maintaining planning models and improving reporting through ERP, planning, and automation tools.

Verify the front end of high-performance RISC-V CPU cores, including instruction fetch, branch prediction, decode, dispatch, and speculative execution. Develop verification strategies, SystemVerilog/UVM testbenches, constrained-random tests, assertions, and functional coverage. Debug RTL and simulation failures using waveforms and collaborate with CPU architects, RTL designers, and software teams to identify root causes and ensure correctness across workloads and corner cases.

Build and lead Tenstorrent’s global supply chain operating infrastructure for hardware products. Own product certification and market readiness, Sales & Operations Planning, global RMA and customer operations, scalable processes, KPIs, dashboards, governance, and cross-functional execution. The role requires developing teams, clarifying ownership, managing ambiguity, and aligning Engineering, Product, Sales, Manufacturing, Quality, Finance, Legal, customers, test labs, and regulatory bodies to support product launches and lifecycle operations.

Leads strategic sourcing for semiconductor design infrastructure, including third-party IP licensing, EDA/CAD tools, vendor negotiations, and complex technology contracts. Develops procurement strategies balancing cost, quality, delivery, and innovation; manages multiple concurrent deals; builds executive-level vendor relationships; and translates technical requirements into sourcing recommendations for leadership. The role supports global engineering teams and AI chip company scale-up operations.