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Lead silicon product and test engineering from tapeout through NPI to volume production. Own ATE strategy, product qualification, OSAT/foundry relationships, and the Bristol validation lab. Build and mentor multidisciplinary test and validation teams, manage budgets and headcount, and align execution with executive strategy across concurrent chip programs.

Serve as the technical interface between Axelera and Taiwan ODM/CM partners, supporting hardware integration, partner bring-up, CM NPI/production support, supplier coordination, component qualification, design verification, and defect triage to enable successful deployment of Axelera accelerator products.

Lead ASIC physical design activities from RTL to GDS including synthesis, floorplanning, place-and-route, CTS, timing optimization, extraction, physical verification, EMIR signoff, and IP integration. Drive automation with Python/Tcl/Bash, debug physical-design challenges, and collaborate closely with architecture, RTL, and verification teams to deliver multi-core in-memory compute SoCs.

Design and implement digital micro-architectures and RTL for AI SoC components, integrate 3rd-party IPs, run static checks and verification, optimize for performance/power/area, automate flows with scripting, and collaborate with verification and physical design teams on DFM/DFT and timing closure.

Lead and build Axelera's AI Infrastructure Systems division to deliver datacenter-class hardware from accelerator cards and OAM/UBB modules to 1U/2U racks. Own architecture, schematics, PCB/layout review, power/thermal/mechanical design, BMC/firmware, bring-up, validation, qualification, NPI, and ramp with CMs/ODMs. Align roadmaps with silicon, SDK, and product teams, engage customers and partners, set engineering processes, manage budget and vendor relationships, and mitigate technical risks through hands-on leadership.

Own platform-level architecture for datacenter AI accelerator systems from server to rack to datacenter. Translate compute, memory, and interconnect requirements into hardware specs; define interconnects, PCIe/CXL integration, power budgeting, RAS/operability, and scalability. Collaborate with silicon, software, AIIS, partners and customers to align architecture and drive platform design best practices.

Lead and scale the digital/RTL design organization to deliver complex AI accelerator SoCs from specification through tape-out. Own RTL implementation, block and top-level integration, enforce coding and review standards, partner with verification/physical design/DFT/software teams, support bring-up and silicon validation, and mentor engineers while contributing to long-term IP and architecture roadmap.

Perform ASIC physical design tasks from RTL to GDS including synthesis, floorplanning, P&R, extraction, timing analysis, CTS, and physical verification. Integrate IPs (memories, I/Os, processors), use EDA tools (PrimeTime, Fusion, Calibre, Redhawk), write automation scripts (Python/Tcl/Bash), debug issues, and collaborate with architecture, RTL, and verification teams.