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Own the integration of IP into ASSP/SOC, including RTL design, synthesis, timing analysis, and verification infrastructure development. Requires expertise in Verilog and C/C++.

Design and verify ASIC chips by implementing RTL, handling synthesis, power estimation, and collaborating on architecture for AI systems.

The Physical Design Engineer will implement AI acceleration SoCs, focusing on RTL-to-GDSII flows, synthesis, timing analysis, and collaboration with internal and external teams.

Develop and execute test automation for AI/ML software releases, troubleshoot issues, collaborate across teams, and maintain QA infrastructure.

The Design Verification Engineer will enhance verification environments for AI SoCs, collaborate on infrastructure, and automate tool flows for verification.

Lead PCIe IP/subsystem and SoC verification: develop SystemVerilog/UVM environments, create constrained-random and directed tests, verify LTSSM, link training, config space, DLL/TLP/PHY interactions, advanced PCIe features, and compliance using PCIe VIP. Build coverage, assertions, scoreboards, debug RTL/UVM, run gate-level simulations, support post-silicon bring-up, and collaborate with RTL, firmware, physical design, DFT, and validation teams.

Design and verify ASIC hardware, optimize designs for power and performance, collaborate on architectural decisions, and support integration activities.

Lead global product marketing strategy and go-to-market for EdgeCortix's AI hardware and software platforms. Shape category positioning, drive product launches, competitive intelligence, partner messaging, and cross-functional alignment while building a global product marketing team and representing the company to customers, partners, analysts, and media.

Lead UCIe IP and SoC verification by developing reusable SystemVerilog/UVM environments, protocol compliance tests, assertions, coverage models, and debug flows. Drive verification closure across subsystem and SoC integration, support gate-level and emulator-based validation, and collaborate with RTL, firmware, physical design, and post-silicon teams during bring-up.