Top Tech Jobs & Startup Jobs

The Senior Emulation Engineer will validate AI accelerator architectures, maintain emulation platforms, develop testbenches, and collaborate on performance optimization and debugging processes.

Lead the DFT architecture and strategy for complex SoCs, overseeing scan/ATPG, MBIST/logic BIST, IJTAG/boundary scan, post-silicon ATE bring-up, and edge-specific IST/POST to ensure manufacturability, reliability, and minimal power/area impact.

Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

Own top-level physical integration and signoff for very large SoCs from floorplan to tapeout. Architect hierarchical physical verification flows, execute full-chip DRC/LVS/ERC/antenna/ESD/latch-up signoff, resolve integration bottlenecks with PD/STA, collaborate with foundries on rule co-optimization, and automate PV/integration flows to accelerate tapeout.

Lead floorplanning and PDN design for complex SoCs, optimizing performance targets and power integrity while establishing best practices.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Lead logic synthesis and signoff for blocks and sub-chips, drive synthesis flow and automation, collaborate with RTL engineers to produce synthesis-friendly netlists, optimize timing/levels of logic, and expand into PNR, STA, and full-chip timing convergence.

The Senior NPU Architect will design and optimize architecture modules for AI accelerators, collaborating with teams to enhance performance for AI/ML workloads.

Lead development and optimization of a highly automated RTL-to-GDSII and timing signoff flow. Own Innovus methodology and Tempus STA integration, reduce turnaround time with Python/Tcl automation, interface with Cadence, debug tool/database issues, and mentor PD and timing teams to ensure robust, high-performance physical implementation for AI accelerators.

Lead SoC-level floorplanning from concept to tape-out for large AI/Data Center chips. Collaborate with architects and RTL leads to optimize PPA, manage bump/package co-design, integrate AMS IPs and high-speed SerDes, design top-level PDN and pin assignments, and develop automated floorplanning workflows (Tcl/Python).