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Lead block-level physical implementation from synthesis and floorplan through CTS, routing, and sign-off. Optimize PPA via deep timing, power, and congestion analysis, automate flows with Tcl/Python, resolve DRC/LVS/IR/timing issues, and collaborate with RTL/DFT teams to left-shift constraints and ensure clean GDSII tape-outs.

Lead full RTL-to-GDSII physical design for sub-5nm SoCs: own full flow, optimize PPA, build scalable push-button methodology, remove execution bottlenecks, and collaborate with RTL/Architecture/DFT/foundry/EDA teams.

Lead and define end-to-end DFT architecture for complex SoCs, including scan insertion, ATPG, MBIST, IJTAG and boundary scan. Drive edge-specific IST/POST strategies, collaborate across design, PD, and yield teams, and lead post-silicon bring-up and ATE debug to ensure manufacturability and reliability.

The Staff DFT Engineer at EnCharge AI will define and implement the DFT architecture for AI accelerators, manage DFT constraints, generate test patterns, and optimize for Edge AI applications while collaborating with ATE teams for silicon debugging.

The Senior Emulation Engineer will validate AI accelerator architectures, maintain emulation platforms, develop testbenches, and collaborate on performance optimization and debugging processes.