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Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

Own top-level physical integration and signoff for very large SoCs from floorplan to tapeout. Architect hierarchical physical verification flows, execute full-chip DRC/LVS/ERC/antenna/ESD/latch-up signoff, resolve integration bottlenecks with PD/STA, collaborate with foundries on rule co-optimization, and automate PV/integration flows to accelerate tapeout.

Lead floorplanning and PDN design for complex SoCs, optimizing performance targets and power integrity while establishing best practices.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

The LLM Inference Deployment Engineer will deploy and scale large language models efficiently on AI accelerators, focusing on model optimization and low-latency inference.

The Senior NPU Architect will design and optimize architecture modules for AI accelerators, collaborating with teams to enhance performance for AI/ML workloads.

Lead development and optimization of a highly automated RTL-to-GDSII and timing signoff flow. Own Innovus methodology and Tempus STA integration, reduce turnaround time with Python/Tcl automation, interface with Cadence, debug tool/database issues, and mentor PD and timing teams to ensure robust, high-performance physical implementation for AI accelerators.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.