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Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Lead floorplanning and PDN design for complex SoCs, optimizing performance targets and power integrity while establishing best practices.

The LLM Inference Deployment Engineer will deploy and scale large language models efficiently on AI accelerators, focusing on model optimization and low-latency inference.

The Senior NPU Architect will design and optimize architecture modules for AI accelerators, collaborating with teams to enhance performance for AI/ML workloads.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.

The role involves architecting production systems for video generation, developing APIs, and establishing production operations to support innovative AI applications.

Lead SOC timing convergence by ensuring high-performance paths to tape-out through cross-functional coordination and advanced analysis of timing issues.

Lead testing strategy for AI accelerators, define DFT architecture, implement testing flows, ensure silicon reliability, and manage cross-functional collaboration.

Lead STA strategy and execution for advanced-node SoC/IP designs, develop novel timing methodologies (MCMM, variation modeling, sign-off margins), act as Cadence Tempus SME, collaborate with RTL/synthesis/physical teams for timing-friendly implementations, and mentor the India team through full-cycle STA to GDS sign-off.