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Seeking a Staff/Sr. Staff Engineer with expertise in RF PLL Design. Responsibilities include leading the development of RF, analog, and mixed signal IPs, designing high-performance RF frequency synthesizers, and collaborating with cross-functional teams. Requires a minimum of MSEE and 7+ years of hands-on experience.

Seeking a Staff/Sr. Staff Engineer in RFIC Design to develop novel SoC products for connectivity and communications. Responsibilities include technical leadership, hands-on contributions, layout supervision, collaborating with cross-functional teams, and participating in post-silicon activities.

Work closely with business teams to understand product requirements and design wireless system solutions. Track standard updates and evaluate feasibility and performance using network simulators. Requires expertise in wireless communication systems, RF technologies, and networking protocols.

Implement MAC and PHY algorithms for low power IoT connectivity devices. Collaborate with cross-functional teams and work on system architecture, Verilog/Systemverilog implementation, and verification.

The Principal Engineer, RF PLL Design will lead the development of RF, analog, and mixed signal IPs. They will design high-performance RF frequency synthesizers and work closely with cross-functional teams. The role requires expertise in RF CMOS fundamentals, transistor-level design, and sigma-delta fractional-N RF PLLs.

The Principal Engineer, RFIC Design will be responsible for the design and development of high-performance custom RF, analog, and mixed signal IPs. The role involves technical leadership, overseeing layout activities, collaborating with cross-functional teams, and performing post-layout simulations and analysis. The position requires strong knowledge of RF CMOS fundamentals, experience in transistor-level design of RF front-end circuits, and familiarity with IC layout and verification.

Join Innophase IoT as a hands-on PHY Verification Engineer/Lead responsible for Low-power WiFi, BT/BLE verification. Duties include developing UVM testbench, test planning, working closely with other engineers, and optimizing design and verification coverage.