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Lead the design and development of high-performance RTL solutions for the Cerebras Wafer Scale Engine, collaborating with teams and managing ASIC vendors.

Design, implement, optimize, and validate high-performance ML and linear algebra kernels for Cerebras hardware. Develop low-level assembly and CSL routines, measure and tune performance, build testing methodologies, and collaborate with chip and system architects to maximize compute utilization for AI and HPC workloads.

Lead the design and development of software systems for manufacturing tests, coordinating with cross-functional teams to enhance efficiency and quality.

The Sr. Technical Staff will validate silicon for wafer-scale engines, conduct high-speed interface testing, and develop automated regression tests. They will collaborate with engineering teams for hardware optimization, diagnosing issues, and ensuring compliance with design specifications.

Join the Kernel Reliability team to improve the reliability of compute clusters, assist in debugging, and enhance system tools alongside hardware teams.

The Senior Operations Accountant will manage cost accounting processes, fixed asset lifecycle, and inventory reconciliations to support financial operations.

Join the Inference Core Model Bringup team to bring up ML models on Cerebras CSX systems, focusing on performance, optimization, and debugging.

Lead a team in developing and scaling distributed inference systems for AI on Cerebras' hardware, ensuring reliability and performance while mentoring engineers.

Develop and execute verification strategies and reusable SystemVerilog/UVM testbenches. Implement tests, manage regressions, collect coverage, and debug issues across simulation, emulation, and silicon bring-up. Collaborate with architects, RTL, physical design, firmware, and software teams to improve verification infrastructure and practices.

The R&D Engineer will design and implement performance workloads on Cerebras' wafer-scale hardware, collaborating across teams to advance AI and scientific computing. Responsibilities include optimizing performance models, contributing to the technology roadmap, and publishing research findings.