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Develop and execute verification strategies and reusable SystemVerilog/UVM testbenches. Implement tests, manage regressions, collect coverage, and debug issues across simulation, emulation, and silicon bring-up. Collaborate with architects, RTL, physical design, firmware, and software teams to improve verification infrastructure and practices.

The role involves collaborating with architects and engineers to develop and implement verification strategies for complex AI chip designs, ensuring high-quality verification processes and methodologies.

The Business Operations Lead will partner with senior leaders to manage operations in the Datacenter organization, ensuring alignment and efficient execution of plans and priorities, while improving transparency and decision-making mechanisms.

As an ASIC Architect at Cerebras Systems, you will translate high-level architecture specs into micro-architecture requirements, conduct performance/power model tasks, engage with SW teams for application modeling, and identify kernel-level hardware acceleration opportunities.

Design and architect front-end network fabrics for AI/ML and HPC clusters. Automate deployment of network infrastructure, debug networking issues, and lead technical projects across teams.

The role involves developing infrastructure for benchmarking AI inference performance, analyzing system behavior, designing telemetry systems, and collaborating with teams to improve feature performance.

The Deployment Engineer will manage AI inference clusters, optimizing deployment, capacity allocation, and ensuring reliability of pipeline operations across datacenters.

Manage AI compute clusters, monitor systems health, optimize resources, and troubleshoot technical issues, ensuring high performance for ML applications.

The Sr. Technical Staff will validate silicon for wafer-scale engines, conduct high-speed interface testing, and develop automated regression tests. They will collaborate with engineering teams for hardware optimization, diagnosing issues, and ensuring compliance with design specifications.

Lead a team in developing and scaling distributed inference systems for AI on Cerebras' hardware, ensuring reliability and performance while mentoring engineers.