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The role involves synthesizing, placing, and routing high-speed designs, collaborating with RTL teams, and optimizing designs for power/performance area.

The Engineering Lead will build a UI-based large-scale management portal for Cerebras clusters, ensuring seamless integration with backend systems and technical leadership. Responsibilities include mentoring a team, collaborating with product management, and delivering a user-friendly tool.

The Senior Performance Analyst will benchmark Cerebras' AI inference performance, analyze competitor pricing, and provide pricing recommendations to enhance the customer value proposition, requiring deep expertise in ML frameworks and architecture.

As a Network Architect, you'll design AI/ML and HPC clusters, address performance bottlenecks, drive multi-team projects, and collaborate with vendors.

Lead the design and development of high-performance RTL solutions for the Cerebras Wafer Scale Engine, collaborating with teams and managing ASIC vendors.

Design, implement, optimize, and validate high-performance ML and linear algebra kernels for Cerebras hardware. Develop low-level assembly and CSL routines, measure and tune performance, build testing methodologies, and collaborate with chip and system architects to maximize compute utilization for AI and HPC workloads.

Develop and maintain the architecture for Cerebras' Inference Cloud Platform, focusing on distributed systems, performance optimization, and technical direction. Responsibilities include coding, design reviews, and mentoring senior engineers.

Design and develop microarchitecture and RTL for wafer-scale AI chips. Lead functional specification, RTL development, synthesis and front-end integration. Collaborate with physical design, verification, DFT, software and systems teams to meet PPA goals. Debug silicon-level functional, timing, and power issues and manage third-party IP and vendor interactions to deliver production silicon.

Design and execute verification strategies and reusable SystemVerilog/UVM testbenches. Implement tests, manage regressions, collect coverage, debug across simulation, emulation, and silicon bring-up, and collaborate with architects, RTL, physical design, firmware, and software teams to ensure silicon-quality designs.

Develop and execute verification strategies and reusable SystemVerilog/UVM testbenches. Implement tests, manage regressions, collect coverage, and debug issues across simulation, emulation, and silicon bring-up. Collaborate with architects, RTL, physical design, firmware, and software teams to improve verification infrastructure and practices.