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The Physical Design Engineer will perform synthesis, timing closure, and integration tasks, collaborating with the RTL team to optimize design flow.

The Performance Engineer - Inference will optimize model inference speed and throughput, debug low-level kernel performance, and develop tools to visualize performance data.

The Head of IT will build and manage the company's technology backbone, focusing on IT strategy, scaling, endpoint management, SaaS governance, and compliance while supporting rapid growth in a high-tech environment.

Lead post-silicon bring-up and optimization of wafer-scale engines: develop debug flows, HW-SW codesign optimizations, build large-scale test infrastructure, create self-checking metrics and instrumentation, and collaborate across silicon, performance, and software teams to improve production performance and release processes.

Build and maintain embedded and system-level software for the wafer-scale AI processor, including administrative services, Linux BSP support, hardware monitoring, diagnostics, and cross-team collaboration to improve reliability and observability.

Design and implement system-level debugging, validation, and observability platforms. Build automated anomaly detection, visualization and analysis tools, and frameworks for failure classification and regression detection. Extend compilers, runtimes, and instrumentation for advanced profiling. Improve bring-up and low-level debug workflows, partner cross-functionally across hardware, firmware, compiler and runtime teams, lead high-impact initiatives, and support incident response and long-term corrective actions.

As an ML Research Engineer, you will adapt and optimize language and vision models for efficient inference on Cerebras hardware, focusing on advanced techniques for low-latency, high-throughput performance.

Lead post-silicon bring-up and performance optimizations for Cerebras Wafer Scale Engines. Develop/debug production-ready flows, instrumentation, and self-checking metrics. Build infrastructure for large-scale silicon workload testing, collaborate with silicon architects, performance and software teams, and streamline CI/CD and release workflows.

Design, develop, and maintain manufacturing test automation from PCBA to system level, build GUIs and web portals, support contract manufacturers, deploy infrastructure, troubleshoot test software and hardware defects, and integrate test data for traceability and yield improvement.

As a 3D Physical Design Engineer, you'll design and analyze 3D integrated products, focusing on ASIC/SoC design, power, clock, and cooling analysis with an emphasis on physical design methodology.