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The role involves designing mixed-signal layouts, collaborating with design engineers, solving layout issues, and utilizing techniques for efficient circuit performance.

As a Physical Design Engineer, you'll implement complex mixed-signal SoCs, optimizing timing and collaborating within a design team, while also developing design methodologies.

Lead the Silicon NPI team to bridge foundry process capabilities and mixed-signal design, resolve SOA/DRC/reliability issues, drive foundry engagement, improve yield and cost, and develop engineering staff.

Design and execute validation tests for pre- and post-silicon products, develop test plans and automation in CI, triage and debug hardware/software issues, and report quality metrics to stakeholders while collaborating with cross-functional teams.

Support and automate mixed-signal IC design flows and EDA/CAD tools, provide methodology and tool support to design/layout teams, develop/automate design methodologies, liaise with tool vendors, and deliver reports to design groups and customers.

Responsible for device characterization and modeling, maintaining lab equipment, and extracting SPICE models for semiconductor devices.

Design and verify high-performance mixed-signal CMOS IC layouts, collaborating with engineers on optimization, layout techniques, and troubleshooting.

Responsible for developing low-power, high-performance ICs in advanced CMOS processes, including design, validation, and post-silicon activities.

Design and develop digital circuit architectures for mixed-signal products, collaborate with engineers, and supervise junior engineers, ensuring high quality IPs.

The Senior Physical Design Engineer will implement RTL to GDS2 physical designs for ASIC projects, collaborate with design teams, and enhance methodologies.