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The Performance Architect will analyze performance bottlenecks in CPU microarchitecture, implement performance models, and optimize workloads for high-performance AI and out-of-order CPUs.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.

Lead the physical design implementation of CPU blocks and cores, optimizing for PPA goals while collaborating with RTL and microarchitecture teams to resolve design bottlenecks.

The Senior Accountant is responsible for accounts receivable, general ledger management, month-end closing, fixed asset maintenance, and improving processes. They ensure compliance and accuracy in financial reporting, collaborating with teams to resolve discrepancies and support audits.

As a Staff Physical Design Engineer, own the physical design of memory cache structures, drive optimizations, solve bottlenecks, and improve methodologies while collaborating with cross-functional teams.

The role involves implementation of NoC and Uncore systems, focusing on PPA optimization. Key responsibilities include leading physical design, driving co-design across levels, and mentoring junior engineers.

Lead the Low Power Verification and Formal Equivalence methodologies, ensuring robust power intent and logical equivalence throughout RTL-to-GDSII flow.

The Staff Design Verification Engineer will lead verification for a cache-coherent interconnect subsystem, focusing on verification planning, execution, and improving methodologies. Key responsibilities include developing robust verification environments and addressing complex verification problems.

The Principal Design Verification Engineer will lead verification strategies, execute high-performance CPU subsystem verification, and improve methodologies, with a focus on CPU core and coherent interconnect verification.