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As a Physical Design Engineer at SiFive, responsible for implementing and optimizing RISC-V CPU's, closing ambitious performance, power, and area goals, collaborating with teams, and contributing to physical design flow development.

Lead implementation and optimization of high-performance Out of Order RISC-V CPU's from RTL to GDSII. Collaborate with microarchitecture and RTL teams to achieve ambitious performance, power, and area goals. Contribute to physical implementation flow development for best automation and PPA.

Drive timing convergence of high performance designs, contribute to timing methodology development, develop timing analysis infrastructure, and work with RTL and physical design teams. Experience in Static Timing Analysis with multiple tape outs required. Strong understanding of timing tools and methodologies.

Seeking a Power Engineer with 3+ years of experience in power simulation, modeling, ASIC power analysis and optimization. Must have strong problem-solving skills and experience with low power architecture and power optimization.

The Staff Verification Engineer at SiFive will be responsible for ensuring the fidelity of new highly configurable cores and other related IPs. They will need to adopt state-of-the-art verification methodologies to in-house designs, create test plans and unit test benches, and ensure verification quality through coverage metrics. This role requires a deep understanding of computer architecture and experience in IP/Component functional verification.

Verification Engineer at SiFive responsible for ensuring the fidelity of new highly configurable cores and other related IPs by adopting state-of-the-art verification methodologies. Requires deep understanding of computer architecture and experience in IP/Component functional verification.

The Principal Verification Engineer at SiFive is responsible for ensuring the fidelity of new highly configurable cores and IPs, adopting state-of-the-art verification methodologies, working closely with design teams, and shaping the verification ground of cutting-edge technologies. They will focus on solving verification challenges in memory subsystems and cache verification. The position requires a deep understanding of computer architecture and significant experience in Core/CPU functional verification.