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The Staff SDET will lead the architecture for automated testing infrastructure, mentor team members, and collaborate with cross-functional teams to ensure system quality in RISC-V embedded products.

The Senior Software Quality Assurance Engineer will design and optimize CI/CD test automation pipelines, lead root cause analyses of test failures, and define key quality metrics for continuous improvement.

Design and implement features in RISC-V CPU cores, collaborate with verification and physical design teams, and document processes.

As a Senior Product Manager, you will articulate SiFive's product portfolio, collaborate with IP architects, and guide Sales during customer engagements. A strong background in product management within the semiconductor industry is required, along with technical marketing and customer interaction experience.

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.

The role involves designing and implementing CPU cores using RISC-V architecture, collaborating with various teams for verification and optimization, and ensuring high-quality design through documentation and teamwork.

The role involves optimizing JVM performance on RISC-V architecture, analyzing CPU and memory efficiency, and collaborating on JIT compiler improvements.

Lead a performance engineering team to research and develop high-performance processor architectures, defining targets and guiding implementation in RTL, while analyzing performance bottlenecks.

Design interconnect IP, architect TileLink interconnect, enhance performance, integrate into SiFive's framework, perform verification, and maintain documentation.

Design and implement debug, trace, and profiling hardware, collaborate with cross-functional teams, and lead improvements in hardware design processes.