Top Tech Jobs & Startup Jobs

Develop and maintain the Verification Platform, collaborate with engineers to create reusable testbench components, and educate teams on best practices.

The Staff Design Verification Engineer will lead verification for a cache-coherent interconnect subsystem, focusing on verification planning, execution, and improving methodologies. Key responsibilities include developing robust verification environments and addressing complex verification problems.

Lead end-to-end verification of complex CPU core microarchitecture using SystemVerilog/UVM. Develop testplans, testbenches, constrained-random tests, scoreboards, checkers, and coverage models. Validate features (OoO, branch prediction, cache coherency, virtual memory), perform ISA-level compliance (RISC-V/ARM/x86), drive regressions, and debug failures across simulation and emulation platforms.

Lead verification planning and testbench development for CPU/RISC-V IP using SystemVerilog and UVM. Create constrained-random tests, write coverage and checkers, debug RTL failures with waveform tools, integrate VIPs, and ensure security-architecture requirements are met.

Design and implement CPU microarchitecture features and ISA extensions using Chisel. Integrate designs into Chisel/FIRRTL framework, perform sandbox verification, collaborate on verification plans, optimize for physical implementation and performance, and document microarchitecture specifications.

Lead verification planning and test strategy for CPU/IP (IOMMU) designs. Develop scalable UVM/SystemVerilog testbenches, write constrained-random stimulus, perform deep RTL debug with waveform tools, drive coverage closure, and integrate third-party VIPs and bus protocols (AXI/AHB/PCIe).

The Senior Design Verification Engineer will ensure functional correctness of SoCs/IPs, focusing on verification plans, environment development, debugging, coverage closure, and mentoring junior engineers.

Architect, design and implement features for RISC-V CPU core generators using Chisel, with responsibilities in verification and performance modeling, collaborating with teams.

Design and implement CPU microarchitecture features and ISA extensions using Chisel; integrate into Chisel/FIRRTL framework; perform sandbox verification and collaborate with verification, physical implementation, and performance teams to meet frequency, area, power, and performance goals. Produce documentation and participate in collaborative design.

Improve and debug the RISC-V Linux kernel for high core-count server systems. Engage with upstream Linux and OpenSBI communities to post and review patches. Debug complex software and hardware CPU/SoC issues in emulation and FPGA platforms. Collaborate with system software, validation teams, CPU architects, and RTL engineers to advance core and system designs.