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The Staff Verification Engineer will ensure the fidelity of new CPU designs by adopting state-of-the-art verification methodologies and creating test plans. Responsibilities include executing tests, analyzing coverage metrics, and developing IP efficiently.

Architect, design and implement features for RISC-V CPU core generators using Chisel, with responsibilities in verification and performance modeling, collaborating with teams.

The role involves analyzing and optimizing power consumption in SiFive IP, guiding architecture for power efficiency, and improving power analysis flows.

Develop and deploy methodologies for measuring and analyzing power consumption of SiFive IPs. Guide teams in designing energy-efficient IPs through power modeling and analysis.

Lead SWQA validation for RISC-V hardware products on pre-silicon platforms (QEMU, FPGA, RTL). Drive test strategy, automation (Python/PyTest/Robot), config management, failure triage, root-cause analysis, and cross-team coordination to improve release readiness and quality metrics.

Lead design verification for out-of-order CPU cores: own DV strategy and execution, architect SystemVerilog/UVM testbenches, develop constrained-random and scenario libraries, define coverage and assertion sign‑off, debug complex OOO and memory/coherence issues, collaborate with RTL/microarchitecture/post‑silicon teams, and mentor junior DV engineers.

Lead verification strategy and execution for CPU-subsystem power-management across unit, subsystem, and signoff levels. Define tests, assertions, coverage, and corner-case stress scenarios for DVFS, retention, clock/reset sequencing, power gating, and multi-domain interactions. Drive debug, root-cause analysis, formal and power-aware methods, reusable infrastructure, and mentor engineers to achieve data-center-grade signoff readiness.

Lead verification strategy and execution for advanced hardware prefetch in high-performance out-of-order CPU cores. Define test plans, checkers, assertions, coverage, and stimulus to validate prefetch training, stream management, request generation, DCache interactions, CSR configurability, and corner cases. Collaborate with architects, RTL, performance, and software teams; apply simulation, formal, emulation, and performance validation; drive debug, coverage closure, and mentor engineering teams to raise DV quality and reusable methodology.

Lead verification strategy and execution for CPU frontend in high-performance out-of-order cores. Define test plans, checkers, assertions, coverage, and stimulus for branch prediction, instruction fetch, redirects, recovery, and MMU/ITLB interactions. Partner with architects, RTL, performance, and verification teams, apply simulation, formal, and emulation methods, drive block- and core-level signoff, mentor engineers, and build reusable DV infrastructure and methodology.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.