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Hands-on system Verilog/UVM development work for modern high-performance CPU verification. Writing test cases and generating targeted tests for RISC-V CPU verification. Collaborating with internal test generators to target coverage/test-plan scenarios.

The Debug, Trace, and Profiling Architect at SiFive will play a vital role in creating silicon at the speed of software across the entire IP portfolio. They will define platform requirements, interact with customers and industry associations, and drive innovation in debug strategies. The role involves defining features, interfacing with customers, and collaborating with various architecture teams.

Lead the development of system software for SiFive development boards, collaborate with internal and external teams, ensure open source practices, and contribute to advanced RISC-V IP features.