Top Tech Jobs & Startup Jobs

As a Physical Flow Software Engineer, you will develop automated flows for SiFive's RISC-V Core IP, collaborating with cross-functional teams to define and implement features. This role focuses on building scalable and reusable tools that interface with physical design tools, ensuring the effective validation of RTL outputs.

The role involves leading a team in power convergence and modeling projects, emphasizing experience in AI/ML accelerators or GPUs. The candidate will conduct power simulation, ASIC power analysis, and optimization while scripting in Python, Perl, or Tcl. Strong communication skills are essential for presenting power status to management and product teams.

The Debug, Trace and Profiling Architect at SiFive will define platform requirements and architectural features for debug, trace, and profiling solutions. They will engage with customers to understand needs, interact with various architectural teams, and develop microarchitecture specifications in a collaborative environment.

The Staff Engineer will focus on hands-on System Verilog and UVM development for high-performance CPU verification, including writing test cases, generating targeted tests for RISC-V CPU verification, and working with internal test generators to achieve coverage and test-plan goals.

The Staff Formal Verification Engineer will implement and maintain formal verification environments, create formal test-plans, and lead the application of various formal verification techniques. Responsibilities include debugging RTL, developing automation scripts, guiding team members, and reviewing proofs with design teams.

The Functional Safety Architect will contribute to SiFive's FuSa/RAS solution portfolio, ensuring seamless integration across IPs and collaborating with engineering and product teams to derive requirements for failure detection and response solutions.

The principal physical design lead is responsible for leading the implementation and optimization of high-performance Out of Order RISC-V CPUs from RTL to GDSII, focusing on performance, power, and area goals, collaborating with teams to drive PPA trade-offs, and contributing to physical implementation flow development.