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Lead verification planning and execution for CPU subsystems, develop scalable testbenches, assertions, coverage, and constrained-random tests. Drive failure analysis, debug RTL/spec/test content issues, close coverage gaps, and improve verification methodology and automation across CPU designs.

Improve and debug the RISC-V Linux kernel for high core-count server systems. Engage with upstream Linux and OpenSBI communities to post and review patches. Debug complex software and hardware CPU/SoC issues in emulation and FPGA platforms. Collaborate with system software, validation teams, CPU architects, and RTL engineers to advance core and system designs.

Architect and implement software and firmware for confidential computing on RISC-V/Silicon platforms. Collaborate with CPU/SoC/security teams, implement TEEs, virtualization and peripheral security solutions, write and review hardware/software specifications, and engage customers, partners, and standards bodies to drive platform security.

The role involves architecting and maintaining the Verification Platform build system, developing tools and build flows, and educating teams on best practices.

The Design Verification Engineer will develop internal processor models and tools, create test cases, and collaborate with teams for verification needs.

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.

The Verification Engineer ensures the accuracy of highly configurable cores and other IPs through state-of-the-art methodologies, test planning, execution, and quality assurance.

Lead the architecture of physical implementation for high-speed CPU designs, focusing on automated ML-driven methodologies and PPA optimization, while interacting with EDA partners.

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.

The role involves designing and implementing CPU cores using RISC-V architecture, collaborating with various teams for verification and optimization, and ensuring high-quality design through documentation and teamwork.