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Develop formal verification plans and properties for RISC-V processors and Chisel-based digital designs. Build verification environments using Chisel, Scala, and Tcl; apply assertion-based, model-checking, equivalence-checking, coverage, and constrained-random methodologies. Analyze formal results, debug failures, improve verification flows, and collaborate with design engineers on architecture and correctness.

Own formal verification strategy and execution for complex out-of-order processor blocks. Identify suitable blocks, create formal test plans, develop Chisel-based verification environments, apply abstraction and proof techniques, debug RTL failures, automate verification scripts, maintain assertion libraries, and guide teams on formal verification tools and methodologies.

Analyzes and optimizes SiFive IP power consumption across architecture, logic, circuit, RTL, and silicon levels. The role develops power models, correlates them with RTL and silicon results, guides performance-power tradeoffs for high-performance out-of-order CPUs, and improves power analysis workflows. Candidates need advanced computer architecture education, 5+ years of power benchmarking and ASIC optimization experience, and strong problem-solving skills.

Own verification planning, execution, debugging, coverage closure, and methodology for high-performance out-of-order RISC-V CPU core components. Develop SystemVerilog and UVM environments, assertions, scoreboards, stimulus, and coverage models. Partner with architecture and RTL teams to identify risks, resolve microarchitectural issues, and achieve signoff quality across frontend, midcore, load-store, execution, vector, and hardware prefetch units. Mentor engineers and improve verification infrastructure and practices across future CPU generations.

Own functional verification for high-performance out-of-order RISC-V CPU core units from block level through core integration. Develop test plans, UVM environments, testbenches, checkers, scoreboards, assertions, constrained-random tests, and coverage models. Debug failures, identify RTL and verification issues, close coverage gaps, and collaborate with architecture, design, performance, and software teams. Contribute reusable verification infrastructure and methodology for future CPU generations.

Staff Design Verification Engineer responsible for planning and executing verification for high-performance out-of-order RISC-V CPU cores, including vector functionality and microarchitectural interactions. Develops verification environments, checkers, scoreboards, assertions, stimulus, and coverage models; leads debug and coverage closure; partners with architecture and design teams; improves verification methodology; and mentors engineers.

Own formal verification for high-performance out-of-order RISC-V CPU cores, including planning, assertions, proof strategies, abstraction, debugging, and signoff closure. Develop scalable formal environments and infrastructure for control, ordering, pipeline, load-store, clock-gating, and microarchitectural behavior. Analyze failures and coverage gaps, collaborate with architecture and RTL teams, improve verification methodology, and mentor engineers.

Staff Design Verification Engineer responsible for verifying high-performance out-of-order RISC-V CPU core functionality, especially ALU and integer execution pipelines. Owns verification planning, test development, debug, coverage closure, assertions, scoreboards, and signoff from block through core integration. Partners with architecture and RTL teams to identify microarchitectural risks and improve design quality. The role also contributes reusable automation and methodology while mentoring verification engineers.

Own formal verification for high-performance out-of-order CPU core units from planning through signoff. Develop assertions, properties, harnesses, proof infrastructure, and abstraction strategies; analyze counterexamples, vacuity, over-constraints, and proof failures; and verify pipeline control, ordering, hazards, forward progress, and clock gating. Collaborate with architecture, RTL, and simulation DV teams, improve formal methodology and automation, and mentor engineers.

Own verification of high-performance out-of-order RISC-V CPU cores, with emphasis on vector functionality and microarchitecture. Develop verification plans, environments, checkers, scoreboards, assertions, constrained-random and directed tests, and coverage models. Debug RTL and infrastructure failures, verify RVV behavior and scalar-vector interactions, close coverage gaps, and collaborate with architecture, design, performance, and software teams to achieve signoff quality.