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The Performance Architect will analyze performance bottlenecks in CPU microarchitecture, implement performance models, and optimize workloads for high-performance AI and out-of-order CPUs.

This role involves developing and maintaining CI/CD test automation pipelines, triaging test failures, analyzing root causes, and collaborating with development teams to ensure quality software and hardware products.

Lead the physical design implementation of CPU blocks and cores, optimizing for PPA goals while collaborating with RTL and microarchitecture teams to resolve design bottlenecks.

The Senior Accountant is responsible for accounts receivable, general ledger management, month-end closing, fixed asset maintenance, and improving processes. They ensure compliance and accuracy in financial reporting, collaborating with teams to resolve discrepancies and support audits.

Design and develop system software including Linux kernel and drivers, collaborate with hardware teams, and debug complex systems for RISC-V processors.

The Staff Software Toolchain Engineer will enhance RISC-V extensions, optimize compilers, and integrate GNU toolchain recipes within a Linux system. Collaboration and high-quality toolchain product delivery are key responsibilities.

As a CPU Design Intern, you will develop RTL for RISC-V cores, gain knowledge in computer architecture, and work on performance and power optimization.

As a Senior Product Manager, you will articulate SiFive's product portfolio, collaborate with IP architects, and guide Sales during customer engagements. A strong background in product management within the semiconductor industry is required, along with technical marketing and customer interaction experience.

As a Physical Design Engineer, you will optimize RISC-V CPU designs and contribute to automation in physical implementation flows to achieve design goals.

Lead the development of SiFive BSPs, creating roadmaps and supporting Yocto-based distributions for various platforms, collaborating with teams and ensuring best open source practices.