Drive DFT strategy and implementation for GPU/SoC designs: scan-based DFT, ATPG pattern generation and analysis, MBIST, IO test planning, and clock DFT/verification. Collaborate with RTL, physical design, verification, and product teams to support pattern simulation, silicon bring-up, manufacturing test debug, and yield ramp. Analyze coverage reports, perform root-cause analysis, and document test methodologies and best practices.