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Experienced FPGA verification engineer responsible for creating testbenches, writing verification plans, debugging RTL bugs, managing regression infrastructure, and developing open-source tools. Must have strong analytical and debug skills, and 4+ years of experience in RTL functional verification for FPGA or ASIC. Experience with Python, Linux, Verilator, and Cocotb preferred. C++ and networking protocols knowledge is a plus. Requires a bachelor's degree in Computer or Electrical Engineering.

As a Market Structure Optimization Engineer at Hudson River Trading, you will analyze network and exchange protocols, automate metrics collection, enhance trading performance, and communicate findings across teams. This role focuses on improving trading infrastructure and minimizing market friction through data-driven methodologies.

As an Exchange Connectivity Analyst, you will analyze network and exchange protocol data, improve trading performance, automate metric visualization, and conduct experiments to optimize trading strategies. Collaboration across teams is essential to minimize latency and enhance the trading infrastructure.