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Seeking an experienced FPGA Verification Engineer to create testbenches, write detailed verification plans, root-cause RTL bugs, collaborate with designers, manage regression, and develop tools. Must have excellent debug and analytical skills, 4+ years of RTL functional verification experience, experience with Python, and familiarity with Verilator and/or Cocotb.

As an Algo Web Engineer at Hudson River Trading, you will build UIs and backend processes to support Algo Developers and Traders in managing research and trading activities. Your work will involve creating tools to visualize and manipulate large datasets, enhancing trading strategies and team collaborations.

Systems Engineer role in Research & Development team at Hudson River Trading, responsible for managing and optimizing distributed compute clusters, automation, troubleshooting, and performance testing. Requires expertise in Linux systems, scripting, and configuration management.

You will develop and maintain software to support developers within the firm, utilizing Python or C++. Responsibilities include managing the complete lifecycle of applications, deploying tooling, and collaborating closely with researchers and engineers to enhance systems.

As a Database SRE, you will design, build, and maintain the database infrastructure for a globally distributed trading system. Responsibilities include configuring PostgreSQL and MySQL servers, improving query performance, implementing monitoring solutions, and applying infrastructure-as-code tools. You will collaborate with a focused team to enhance database infrastructure supporting real-time workflows.

As a Systems Engineer at Hudson River Trading, you'll enhance the performance and maintainability of Linux research systems, manage large-scale distributed compute clusters, automate technical infrastructure, troubleshoot issues, and improve productivity in a collaborative environment.

Experienced FPGA Verification Engineer responsible for creating testbenches and tests for FPGA platform, writing verification plans, debugging RTL bugs, and managing regression infrastructure. Strong background in RTL functional verification for FPGA or ASIC required. Experience with Python, Linux, and code coverage analysis desired.