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Responsible for developing custom SRAM and register file memories, enhancing circuit performance, optimizing power, and collaborating across teams.

The SoC Fabric Architect will define and optimize fabric architectures, collaborate with multi-disciplinary teams, and analyze trade-offs for system performance and power goals.

As a SoC Performance Modeling Engineer, you will design and implement performance models, validate them, analyze performance studies, and enhance modeling infrastructure.

The SoC Performance Modeling and Verification Engineer will validate performance models against specifications, develop test suites, and debug performance issues in Rivos SoCs, collaborating with architecture teams.

Lead the microarchitecture design for power management and debugging features, ensuring integration with various teams to meet design requirements.

Responsible for verifying DDR and HBM memory subsystem designs, developing test plans, integrating IPs, and supporting debug efforts across teams.

The engineer will verify features of DDR and HBM memory subsystems, develop test plans and testbenches, and support debug processes.

As a Memory Controller Verification Engineer, you'll verify DDR and HBM memory subsystems, develop test plans, and collaborate with design teams and vendors.

Lead performance analysis and optimization for silicon systems, collaborating with cross-functional teams on workloads, power, and architectural decisions.

Intern will be responsible for physical design from RTL to GDSII, collaborating with teams for design validation and optimization.