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Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories, optimize power and performance metrics, and support silicon bring up. Responsibilities involve circuit design, simulation, equivalence checking, PPA analysis, and collaboration with cross-functional teams.

As a Memory Controller Verification Engineer, you'll verify the digital logic aspects of DDR and HBM memory subsystems, develop test plans and testbenches, integrate verification IPs, and collaborate with design teams and third-party vendors. You'll also engage in debugging and regression activities, ensuring robust memory interface performance.

The Silicon Physical Design Verification Manager will develop PDV methodology and infrastructure for verifying large SoCs, ensuring quality integration across design teams and driving convergence at both full chip and sub-block levels, while managing a team of engineers to meet project milestones.

Seeking a Senior Memory Design Engineer with 10 years of custom circuit design experience to drive the design and development of SRAM, register file, and custom cells for high performance and low power designs. Responsibilities include working with microarchitecture team, conducting PPA analysis, design equivalence checking, collaborating with CPU and SoC physical design teams, and interacting with technology and CAD teams.

Responsible for internal interconnect architecture specification and performance optimization. Collaborate with Silicon team members and industry consortiums. Develop, assess, and refine architecture to meet power, performance, and timing goals.

The Senior Memory Design Engineer will develop custom SRAM and register file memories to enhance circuit performance while optimizing power. Responsibilities include designing custom circuits, conducting PPA analysis, collaborating with various teams for design implementation, and ensuring high-quality design collateral. A solid background in circuit design and low power techniques is essential.

The Fabric/Interconnect Architect will design and specify internal interconnect architectures for computing platforms, focusing on both coherent and non-coherent interconnects. They will collaborate with the silicon team on performance, power, and area specifications, ensuring high-level architectural goals are met through detailed design and validation plans.