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The role involves owning physical design integration at sub-system or full chip level, working on design closure and collaborating with CAD teams.

Develop and drive power modeling and optimization for CPU and SoC blocks. Collaborate with design and verification teams to analyze and reduce power consumption while managing trade-offs.

Develop and drive power modeling and optimization for CPU and SoC blocks, focusing on power reduction and performance analysis, while collaborating across teams.

The Floating Point & Logic Design Engineer will develop microarchitecture, refine RTL designs, validate physical designs, and support verification processes for high-performance components.

Design and validate power systems for chip boards, collaborate with teams to ensure electrical and thermal requirements are met, and conduct testing and debugging.

The Senior Memory Design Engineer will develop custom SRAM and register file memories, focusing on performance and low power design while collaborating with various teams.

Analyze and improve performance for deep learning workloads, develop analytical models, and validate performance for AI computing platforms.

Perform post-silicon power activities including power validation, workload analysis, and cross-functional collaboration to optimize power performance ratios.

Develop state of the art custom SRAM and register file memories, focusing on circuit performance, low power design, and silicon bring up.

The DFT Engineer will define DFT strategy, design DFT features, validate requirements, and collaborate with teams to ensure effective test coverage and debug observability.