Top Tech Jobs & Startup Jobs

Develop physical layouts and design implementations for ASIC products, including power grids, 2.5D and 3D die-to-die interconnects, ubump and RDL patterns. Perform DRC, LVS, electrical checks, signal and power integrity analysis, and process automation using TCL and Python. Evaluate advanced interconnect technologies, support customer products, and contribute to technology and testchip roadmaps while collaborating with R&D, customers, manufacturing partners, and global teams.

Designs and supports semiconductor timing solutions using static timing analysis, physical design principles, timing constraints, signal integrity, clock networks, and timing models. Debugs timing-tool errors, generates reports, analyzes setup and hold timing, and works with large datasets. Collaborates independently with geographically distributed engineering teams, manages multiple assignments, communicates findings clearly, and may supervise others. Requires extensive electrical or computer engineering experience and TCL programming.

Architect and develop reusable ASIC verification environments using SystemVerilog and UVM/VMM. Create test plans, functional coverage, and pseudo-random tests for block, core, and SOC designs. Debug regression failures, close coverage gaps, document verification strategies, improve verification quality and efficiency, collaborate with design and architecture teams, and mentor junior engineers through the ASIC lifecycle from architecture to tapeout.

Leads board hardware design projects from requirements through schematic creation, simulation, layout coordination, validation, bring-up, debugging, and engineering changes. Collaborates with architects, product managers, mechanical and physical design engineers, signal integrity teams, firmware, validation, customers, and contractors. Designs high-speed PCBs and DC/DC regulator circuits, manages components and bills of materials, writes functional specifications and test plans, and supports multiple concurrent assignments.

Design high-Q FBAR filters and multiplexers for 5G and Wi-Fi RFFE solutions. Own acoustic resonator synthesis, die layout, floor planning, package integration, module co-design, and 3D electromagnetic simulations. Perform yield, Monte Carlo, and corner analyses for high-volume manufacturing. Collaborate with process, modeling, test, module, and design teams to correlate simulations with lab data. Requires advanced RF/microwave expertise and a record of tape-outs or high-volume product releases.

Develop and sustain dry etch processes for silicon-based MEMS technologies in R&D and high-volume manufacturing. Responsibilities include evaluating materials and applications, optimizing and controlling processes, conducting DOE and data analysis, resolving yield and defect issues, documenting improvements, transferring processes into production, and collaborating with engineering, operations, and equipment maintenance teams.

Lead and manage customer ASIC programs from RFQ through production. Advise on EDA flows, perform physical design and STA checks, assess risks, coordinate cross-functional mitigation, and support tape-out quality. Engage with customers and internal teams on IP, packaging, test, and production, and mentor teams on best practices.

Perform measurement, evaluation, and analysis of RF components, including power amplifiers, low-noise amplifiers, and SOI switches, to develop performance improvements. The role requires deep RF expertise and familiarity with industry standards such as 3GPP specifications.

Lead design and verification of integrated circuits and ASIC development across architecture, logic, simulation, synthesis, place-and-route, timing and power analysis. Owns complex project delivery, mentors junior engineers, evaluates process flows and vendor capability, and drives documentation and experimental validation for new products and processes.

Lead architecture and design of high-performance clocking solutions. Manage full lifecycle of analog timing IPs and validation, ensuring integration into SoCs.