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The Staff Engineer I - Physical Design will handle physical design and verification tasks for ASIC development, including floor-planning, timing closure, and IR/EM analysis. The role involves mentoring junior team members and ensuring the integration of different design components. Reporting to the ASIC Design Director, the engineer will work in a hybrid environment managing project-specific workflows.

Responsible for verification of IP, Block, or Subsystem at SoC Level, generating documentation, debugging verification tasks, and developing the verification environment and components. Requires a strong understanding of functional verification and experience with various interfaces and methodologies.

The Principal Engineer - SOC Verification is responsible for verifying IP, Block, or Subsystem at SoC Level, developing and owning the verification environment, and generating necessary documentation. The role requires an understanding of the verification flow, experience with digital verification aspects, and proficiency in various protocols and scripting languages.