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The ASIC Design Engineer at Axiado will work on developing and implementing SoCs, optimizing performance and power, collaborating with various teams, and supporting chip validation until production maturity. The role requires expertise in RTL logic design, synthesis, micro-architecture specifications, Verilog coding, and interface protocols like PCIe, USB, and more. The candidate should have experience with tapeout, FPGA debugging, and working with repository management and bug tracking tools.

Architect System-on-Chips for next generation infrastructure products, develop innovative platform and software specifications, collaborate with industry technologists, and drive standards in open source eco-systems.

Verification Engineer position at Axiado, responsible for RTL SoC/Subsystem verification of ARM based SoCs. Key responsibilities include project leadership, test plan definition, RTL verification, system level verification, and collaboration with various teams. Requires 8+ years of experience with UVM verification, test plan definition, RTL and gate-level simulation, coverage analysis, scripting languages, and BE/BTECH or ME/MTECH in EE/EECS/CS.