Top Hardware Engineer Jobs

The Senior Hardware Reliability Engineer ensures product reliability through planning, testing, and collaboration across engineering and operations. Responsibilities include leading investigations, analyzing failure data, and designing reliability strategies throughout the product lifecycle.

Design, develop, integrate, and test hardware for autonomous maritime vessels. Support prototype builds, field tests, troubleshooting, and DoD technical deliverables while working cross-functionally in a fast-paced startup.

Lead the hardware engineering team in developing robust systems for wireless power transfer, overseeing design, integration, and testing processes.

Mid-level hardware engineer supporting DoD command-and-control system integration. Duties include solid modeling, engineering drawings, BOM and MBOM creation, coordinating design with manufacturing, supply chain and logistics, tracking production status, and serving as liaison between program management and functional teams. Requires MRP/SAP experience and a DoD Secret clearance (or ability to obtain).

Design and develop integrated hardware test solutions including console and panel layouts, power/cooling monitoring, RF and electronic circuit design. Support SW/HW integration, requirements verification, lab testing, anomaly investigation, and documentation. Lead technical work while ensuring cost, schedule, and producibility constraints are met.

Design and verify integrated hardware and test solutions including console, panel, power/cooling, RF, and electronic circuits; support SW/HW integration, ATE design, troubleshooting, anomaly resolution, and requirements verification for classified defense programs.

Design and verify integrated hardware and test solutions (console/panel layouts, power/cooling, RF, analog/digital). Develop and integrate SW/HW test systems, use lab test equipment, troubleshoot anomalies, support requirements verification, and work with ATE and schematic/layout tools. Position requires U.S. citizenship, ability to obtain Secret clearance and Special Program Access; on-site in Waynesboro, VA with ~10% travel.

Design and develop next-gen HMI hardware: define architecture for SoC-based modules, create schematics and PCB layouts, perform SI/PI/thermal analysis, design and calibrate sensor boards, run bring-up and lab/field/EDVT testing, support global certification (FCC/IC/CE), and coordinate fabrication, assembly, and integration.

Design and develop next-gen HMI hardware: specify SoC-based architectures, create schematics and PCB layouts, perform SI/PI/thermal analysis, design and integrate sensor boards, run bring-up and lab/field testing, and support global certification (FCC/IC/CE). Coordinate fabrication, assembly, and testing with cross-functional teams.

Provide strategic technical leadership for board-level hardware design across defense and aerospace programs. Architect high-speed digital boards (400G+ Ethernet, PCIe Gen5+, DDR5+), drive design-for-manufacturing/test, lead proposals and BOE, mentor engineers, and champion signal integrity, EMI, and reliability practices for ruggedized mission-critical systems.

Lead design and development of ruggedized board-level hardware for defense/aerospace systems. Architect high-speed digital boards (FPGAs, secure processing, PCIe, DDR5, 400G Ethernet), establish design standards, ensure manufacturability and verification, support proposals, and mentor engineering teams through production.

Lead hardware engineering efforts for the C2BMC missile defense program, supporting hardware architecture, BOM management, procurement, EOS/EOL analysis, and CDRL delivery. Coordinate with architecture boards, logistics, and cross-functional teams to select, baseline, and evaluate COTS hardware and network devices while maintaining security and program-specific requirements.

Lead hardware system test and integration activities including test planning, environment development, unit and assembly testing, troubleshooting and hardware modifications, test software/hardware design, documentation, drawings, rack-and-stack, and RF/compute integration for field deployments. Requires occasional CONUS/OCONUS travel and work in austere conditions.

Lead hardware integration and test engineering for ground systems: plan tests, develop test environments, design test software/hardware, troubleshoot and modify hardware, document designs and validation plans, generate drawings, rack and integrate RF and compute equipment for deployment, and support field activities including occasional CONUS/OCONUS travel.

Lead hardware development for next-generation enterprise storage: architect systems, design PCBs, validate and automate hardware tests, perform failure analysis with oscilloscopes and bus analyzers, and ensure power, SI, and thermal integrity for high-speed interfaces.

Lead triage, root cause analysis, and resolution for PCIe/NVMe/SMBus issues across chip bring-up, manufacturing, and field. Develop validation test plans, run failure analysis, automate triage with AI tools, document findings, and mentor junior engineers. Work primarily on-site in Santa Clara.

Design, validate, and sustain enterprise storage hardware from schematic capture through PCB layout and production. Lead hardware validation, automate subsystem test plans (CPU, DDR, PCIe, Ethernet), drive product introduction with manufacturing partners, perform failure analysis, and support customer escalations to ensure reliable, high-performance storage systems.

Design and analyze electronic hardware and firmware for radar and high-power systems. Develop circuit board designs, requirements, test plans, and support test events. Conduct trade studies, troubleshoot electronics, and produce technical documentation to meet customer and contract requirements.

The Hardware Engineer will design, validate, and improve electronic systems for automotive applications, collaborating with internal teams and customers to resolve technical issues and enhance product performance.

Develop and validate block-level and full-chip SDC timing constraints and perform STA to identify and resolve timing issues. Collaborate with front-end and back-end teams on clocking, timing exceptions, and physical design closure. Optionally perform RTL design or IP integration and contribute to full-chip clocking documentation and SDC methodology to ensure correctness early in the design cycle.

Lead hardware quality strategy and complex root-cause investigations across switching, routing, and AI data center products. Champion defensive design, corrective actions, and large-scale data/AI analysis of field telemetry to prevent systemic failures. Advise executives, represent quality commitments to customers, and mentor engineering teams to raise reliability standards.

Design and validate server subsystems, ensure designs meet functional specifications, create technical documentation, collaborate cross-functionally, manage JDMs, and deliver quality hardware products on time.

Lead experimental R&D to design and prototype quantum networking hardware (entanglement sources, switches, transduction). Collaborate cross-functionally, run tabletop and on-site tests, analyze results, publish papers, supervise postdocs and interns, and help transition prototypes into products and demos.

Design, validate, bring-up, and debug enterprise switching hardware for the Catalyst 9300 series. Drive manufacturability, reliability, and cost decisions; collaborate with cross-functional teams on signal integrity, power, thermal, EMI/EMC, compliance, manufacturing readiness, and sustaining support.

The role involves architecting high-performance semiconductor memory test equipment, driving strategic development, collaborating across teams, mentoring, and influencing technical decisions to enhance testing infrastructure.