Top Design Engineer Jobs in Bangalore

Lead end-to-end physical implementation of large, high-performance SoCs from floorplanning through GDS signoff. Drive strategy, timing closure, power and signal integrity, PPA optimization, cross-functional coordination, and mentor senior engineers to meet aggressive frequency, power, area, and schedule targets.

Lead verification strategy and execution for UA Link Switch SoCs: define methodology, build UVM/SystemVerilog testbenches, drive coverage and regression, debug issues, mentor engineers, and lead sign-off for first-silicon readiness.

Perform functional verification of mixed-signal IPs, build verification plans and testbenches, run simulations, analyze power/timing, debug failures, conduct root-cause analysis, and collaborate with digital/analog architects to improve designs and verification infrastructure.

Lead development, testing, and maintenance of a cloud-native supply chain data platform. Design and implement scalable microservices, translate requirements to stories, triage and fix incidents, collaborate in Agile rituals, improve reliability and automation, and mentor peers while ensuring secure, cost-efficient cloud solutions and operational readiness.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.

Build and enhance core hardware validation frameworks for Cisco Silicon One ASICs. Design and automate end-to-end validation tests across hardware, simulation, and CI/CD. Develop scalable Python/pytest test frameworks, validate networking features (packet processing, QoS, ACLs, warm boot), debug hardware/software issues, and collaborate with silicon, SDK, and architecture teams to ensure product quality.

Verify mixed-signal logic components and IPs through functional verification, develop verification plans, testbenches and environments, run system simulations, debug presilicon failures, analyze power/timing, and collaborate with digital/analog/physical design teams to improve architecture and verification infrastructure.

Lead end-to-end SoC/IP verification: define IP-level strategies, build reusable UVM testbenches, drive functional/code/assertion/cross-coverage closure, apply AI/ML for coverage convergence, debug in simulation/emulation/post-silicon, collaborate across RTL/architecture/emulation teams, mentor engineers, and support GLS and low-power verification.

The role involves functional logic verification of FPGA designs, developing verification plans, executing tests, analyzing designs for power and timing, and collaborating with various teams to enhance verification processes.

The engineer conducts FPGA logic verification, develops verification plans and test benches, runs simulations, debugs issues, and improves methodologies to ensure design specifications are met.

The Senior Staff Verification Engineer collaborates to develop verification strategies, creates test plans, and implements verification environments; ensuring design functionality and robustness through testing and debugging.

Provide technical consultation and support for Cadence's digital & sign-off tools to customers, assisting in design implementation and problem-solving. Mentor a team and author knowledge content while driving product improvements based on customer feedback.

Drive physical implementation and timing closure for high-performance chip designs. Architect advanced clock distribution and global interconnects, optimize RC/jitter/IR issues, collaborate with RTL/architecture teams, mentor engineers, and sign off on implementation using industry EDA tools.

Develop and maintain a scalable Verification Platform including VIPs, AIPs, and testbench components. Architect libraries in Scala/Chisel, build SystemVerilog/UVM VIPs, create test plans and testbenches, and educate DV teams on best practices.

Lead end-to-end physical design (synthesis, floorplan, P&R, signoff) for complex IPs, co-optimize RTL and microarchitecture to meet aggressive PPA targets, solve timing/routing/IR issues, apply advanced techniques across product classes, and mentor junior engineers.

The Digital Design Engineer will design integrated solutions for industrial automation, covering system architecture, RTL design, verification, and participate in technical initiatives, mentoring juniors.

Lead RTL design and micro-architecture for complex IPs and subsystems in MCU SoCs. Drive PPA targets, support SoC integration, own design quality (lint, CDC, RDC), collaborate across teams, mentor junior engineers, and improve RTL methodologies and flows.

The role involves defining verification strategies, leading verification activities, developing verification environments, debugging RTL errors, and mentoring engineers in IC verification projects.

Perform functional verification of mixed-signal IP: create verification plans and testbenches, run system simulations, analyze power/timing, debug presilicon failures, drive corrective fixes, and collaborate with analog/digital/physical design teams while maintaining verification infrastructure.

Provide technical leadership for Ethernet IP bring-up, validation, and customer support across 10G–100G speeds. Debug designs, validate protocol compliance (AN/LT, IEEE 1588 PTP), create reference designs and documentation, collaborate with cross-functional teams, and drive root-cause analysis to transition designs from prototype to production.

Provide customer-facing technical leadership for Ethernet FPGA IP: lead design bring-up and validation across 10G–800G, debug and optimize performance, validate protocol compliance (AN/LT, IEEE1588 PTP), produce reference designs and documentation, and collaborate with design, validation, product engineering, and sales to resolve issues and improve IP quality.

The role involves SOC/Subsys verification, developing UVM-based testbenches, mentoring junior engineers, and conducting verification reviews.

Develop and execute IP-level verification plans, build and maintain testbenches and UVM/OVM environments, run functional/system simulations, debug failures, analyze power/timing impacts, document results, and collaborate with architects, RTL and physical design teams to improve verification frameworks and infrastructure.

Lead pre-silicon verification for complex SoC designs, define verification strategies, and collaborate cross-functionally to ensure system correctness and quality.

The Staff Design Verification Engineer will lead verification strategies for complex designs, mentor junior engineers, and resolve verification challenges while representing the company to customers and partners.