Top Design Engineer Jobs in Bangalore

Perform block- and full-chip static (IR) and dynamic (IVD) sign-off; power estimation (vector and vectorless); signal and power EM sign-off; implement custom power grids; conduct system-level PDN analysis across board, package, interposer, and die; collaborate with SoC and packaging teams on bump assignment and package routing optimization; run vectorless, vector, and mixed-mode dynamic analyses and PG grid resistance checks.

The Principal Design Engineer will perform functional verification of the DDR Subsystem, ensuring high quality and adherence to technical requirements, while mentoring team members and improving verification processes.

Design, implement, and integrate complex analog circuits for advanced DRAM products, managing layouts, verification, and mentoring junior designers while collaborating across groups.

The Principal Design Engineer will manage design verification for interconnect IP, craft and execute verification plans, and collaborate with cross-functional teams.

Lead SoC design execution across cross-functional teams, drive SoC assembly, quality checks, connectivity signoff, lint/CDC, bug triage, code reviews and ECOs. Participate in silicon architecture and micro-architecture reviews, collaborate with IP teams, support IP selection and licensing, and hire/mentor SoC design engineers while improving design processes and tools.

Leads full-chip ASIC physical design for large programs, including implementation strategy, PPA optimization, closure, signoff readiness, and tapeout delivery. Defines physical design flows, methodologies, guidelines, and adoption plans; resolves design and flow issues; drives technology adoption and organization-wide improvements. Collaborates with front-end, layout, EDA, and program teams, represents physical design in program forums, maintains vendor relationships, hires and mentors engineers, and coordinates execution across teams.

Architects, develops, debugs, tests, and maintains digital SOC design methodologies and EDA flows from RTL through GDS. Creates scripts, qualifies commercial EDA tools, verifies flow signoff, and establishes tool regressions. Collaborates with engineering IT, database, technology, and design teams to optimize compute infrastructure and resolve signoff issues. Leads projects, guides engineers, documents methodologies, trains design teams, supports flow setup, and drives consensus across business units and EDA vendors.

Develop, maintain, debug, test, and qualify SoC design methodologies and EDA flows from RTL through GDS. Implement scripting-based workflows, verify flow signoff results, establish tool regressions, and integrate flows with engineering compute infrastructure. Support design engineers by resolving setup issues, documenting methodologies, training teams, and collaborating with IT and database management groups.

Leads ASIC design verification across IP, subsystem, and SoC levels. Defines test plans, develops reusable UVM environments, drives functional and code coverage closure, debugs complex issues, and owns verification deliverables through sign-off. Applies AI-assisted workflows to improve test generation, debug, coverage analysis, and regression efficiency. Collaborates with architecture, design, validation, and cross-functional teams while advancing verification automation, quality, and process improvements.

Lead SoC design and integration for networking DPUs and switch silicon. Define project milestones, develop system-level methodologies and IP, coordinate cross-functional teams, integrate subsystem pieces, and deliver models for verification across cluster/subsystem/SoC/emulation stages.

Design and develop conveyor and automated material handling systems using SolidWorks. Collaborate with teams, perform calculations, and create technical documentation.

Seeking a Public Health Engineer with 10+ years in design for plumbing and firefighting for building and industrial projects. Must know NFPA and NBC rules and have experience with Revit.

The Principal Design Engineer will be responsible for the design verification of IPs, including developing UVM testbenches and formal verification.

The role involves IP integration, verification, and release, focusing on RTL integration and debugging, with significant required experience in design processes.

The Principal DFT Design Engineer will mentor junior engineers, lead DFT projects, use EDA tools, and drive innovation in testing methodologies.

The Design Engineer II will perform post-silicon physical layer electrical validation, manage teams, and lead validation efforts for high-speed SERDES protocols.

This role involves design verification for IP development, requiring expertise in UVM testbench development and formal verification processes for various interface designs.

The role requires a Sr. Principal Design Engineer with extensive experience in RTL design and development, particularly using Verilog and System Verilog, to solve complex engineering challenges.

The Principal Design Engineer will develop high-performance physical IP for industry-standard protocols, focusing on digital architecture, low-power design, and collaboration with teams.

The role involves leading design verification projects, developing functional verification environments, and ensuring complex designs meet specifications using System Verilog and UVM.

The role involves DFT project leadership, test architecture definition, RTL changes, scan insertion, and customer interaction, while mentoring junior engineers.

Design and assist customers with semi-custom ASICs, FPGAs, and electronic systems. Responsibilities include development, testing, and debugging of designs and systems, while providing technical support to clients.

Lead the architecture, microarchitecture, RTL development, IP integration, and silicon delivery of complex processor-based SoCs for smart analog and sensor products. Drive performance, power, area, safety, security, timing, and integration objectives from concept through tapeout and silicon bring-up. Provide technical leadership across RTL, verification, DFT, physical design, and software teams; mentor engineers; resolve cross-functional issues; define reusable platform architectures; and lead technical reviews and design signoffs.

Lead the RTL implementation or verification of microprocessor cores, manage timing, area, and power goals, and collaborate with various design teams.

The BIM Design Engineer will create BIM models for ELV systems, conduct clash detection, and ensure compliance with building codes while collaborating with project teams.