Top Design Engineer Jobs in Bangalore

The Lead Product Engineer is responsible for RTL coding, micro-architecture design, and ASIC development, along with formal verification processes.

The FPGA Silicon Design Verification Engineer performs verification of FPGA designs, develops verification plans, analyzes simulations, debugs issues, and collaborates with teams to ensure functional compliance.

Lead block-level digital designs and verification, optimize for timing and power, mentor junior engineers, and interface with customers.

The Staff Design Verification Engineer is responsible for planning and verifying designs using SystemVerilog and UVM, creating verification plans, and mentoring junior engineers.

As a Digital Design Verification Engineer, you will validate designs for mixed signal electronic components, perform tests, and analyze results to ensure compliance with specifications, while collaborating with cross-functional teams.

Lead product engineer responsible for product development, verification expertise in memory protocols, driving product adoption, and collaborating across teams to meet customer needs.

Lead development of next-generation mixed-signal design automation flows, collaborate with analog IC teams to deploy AI-powered tools, mentor staff, and integrate external CAE tools with ADI internal capabilities.

Lead digital microarchitecture and RTL design for next-generation PMICs and Intelligent Power Systems. Own architecture-to-tapeout flow, create new IP, design complex state machines, power sequencers, control loops, perform CDC/lint/power analysis, silicon debug and root-cause, and mentor team while integrating mixed-signal blocks and communication protocols.

Develop and execute verification plans and UVM-based testbenches to validate RISC-V CPU microarchitecture. Perform functional coverage analysis, system-level simulations, debugging, automation with scripting, and collaborate with architects and RTL designers to close verification gaps and improve verification infrastructure.

Build and maintain FPGA prototyping platforms for ASIC designs, owning the Vivado synthesis/implementation flow, porting RTL to FPGA, closing timing on large designs, automating build scripts (TCL/Python), collaborating with design/validation teams, supporting silicon validation with FPGA images, and developing bare-metal test programs.

Lead chip-level planning and perform block- and leaf-cell custom layouts for CMOS/BiCMOS. Drive schematic-driven layout, floorplanning, power planning, DRC/LVS/ERC verification, chip integration and tape-out. Mentor junior and offshore layout engineers, develop cross-site methodologies, and improve layout processes and automation.

The Principal Engineer - Design leads architecture and micro-architecture for complex ASIC designs, ensuring quality and performance while mentoring engineers. Responsibilities include driving RTL design execution, resolving design challenges, and collaborating with various teams on data center solutions.

Design and develop RTL for various digital components, work on micro-architecture, and collaborate with verification teams. Automate design tool flows as necessary.

The Senior Staff Engineer will lead ASIC design processes, define standards, collaborate with teams, and mentor junior members, focusing on complex SoC architectures.

The Staff Design Verification Engineer leads verification strategies for complex designs, mentors junior engineers, collaborates across teams, and resolves verification challenges.

As a Staff Design Verification Engineer, lead the verification strategy for complex designs, mentor engineers, and ensure product quality through advanced methodologies.

The role involves leading and deploying emulation and FPGA prototyping tools, supporting product line verification, and engaging with EDA vendors for improved methodologies.

The role involves verification and modeling of mixed signal designs, defining test plans, and collaborating with product development teams.

Lead the development of verification strategies for mixed-signal designs, mentor junior engineers, and ensure product quality through sophisticated UVM-based environments.

The Senior Engineer will design and develop analog circuits, focusing on power delivery applications, and execute full-chip projects, contributing to product innovation.

Design and develop analog circuits, focusing on power delivery applications, while collaborating with teams on full-chip execution and analog design concepts.

The role involves designing and developing analog circuits, especially for power delivery applications, with emphasis on high voltage products and full-chip execution.

Perform functional logic verification for integrated SoCs: develop verification plans, testbenches, and emulation/system-simulation environments; execute tests, debug presilicon issues, document plans, and improve verification infrastructure using postsilicon learnings.

Lead RTL design and micro-architecture of complex IPs/subsystems for MCU SoCs. Drive RTL quality (lint/CDC/RDC), support synthesis/simulation/STA, collaborate across teams for SoC integration, mentor juniors, and improve RTL methodologies.

Verify ASIC memory subsystem designs for GPUs/SOCs using advanced methodologies (SV/UVM). Define verification scope, develop infrastructure, create test plans, build BFMs/monitors/checkers/scoreboards, run coverage-driven verification, and collaborate with architects, designers, and silicon teams.