Top Design Engineer Jobs in Bangalore

The Principal Digital Design Engineer defines technical strategy for digital design, leads complex SoC architecture development, drives innovation in methodologies, mentors talent, and represents the company as a technical authority.

Design optimized digital blocks, develop TCL scripts, ensure compliance with specifications, support DFT strategy, conduct verification planning, and produce documentation.

Lead and own verification of complex SoC/IP designs: plan verification strategies, develop environments and tests (UVM/C++), run/debug simulations/emulations, apply random-stimulus and coverage-driven techniques, mentor engineers, and improve verification methodologies and tools to ensure silicon-quality delivery.

Define and lead verification strategy and plans, develop SystemVerilog/UVM environments for blocks and SoCs, coordinate verification activities, debug RTL functional issues, and improve verification methodology.

Lead verification strategy and plans for mixed-signal IP and SoC blocks. Develop SystemVerilog/UVM environments, coordinate verification activities, debug RTL functional issues, collect coverage, manage regressions, and improve verification methodology.

Lead verification strategy and plans for blocks and SoCs; develop SystemVerilog/UVM environments; coordinate and lead verification activities; debug RTL functional issues; improve verification methodology and manage coverage and regressions.

Lead and define verification strategies and plans for digital/SoC blocks, develop SystemVerilog/UVM environments, debug RTL functional issues, coordinate verification activities, and improve verification methodology.

Perform functional verification of FPGA designs by developing verification plans, testbenches, and environments (UVM/OVM). Run simulations, analyze power and timing, debug pre-silicon issues, and collaborate with architects, RTL and physical design teams. Maintain verification infrastructure, execute gate-level and power-aware strategies, and document verification results and reviews.

Develop and execute functional verification plans and testbenches for FPGA designs using SystemVerilog and UVM/OVM. Create verification environments, run simulations (including gate-level and power/timing-aware), root-cause and debug pre-silicon issues, collaborate with architects and RTL/physical design teams, and document verification strategy and results.

Lead SoC execution from specification to silicon: define SoC architecture and product strategy, select IP and foundry nodes, drive PPA optimization, govern silicon sign-off, and coordinate cross-functional teams (design, verification, DFT, PD, power, SiVal) to deliver first-time-right silicon.

Lead analog/mixed-signal architecture and delivery of HBM PHY solutions (HBM4) for high-speed AI/HPC systems. Own TX/RX, clocking (DLL/PLL), training/calibration, SI/PI budgets, AMS modeling, silicon bring-up, and cross-functional integration across packaging, physical design, and system teams to ensure robust, silicon-proven high-bandwidth interfaces.

Lead mechanical product development for industrial instrumentation from concept through validation and release. Design for manufacturability, select materials, perform load and strength calculations and simulations, ensure compliance with safety/industry standards, collaborate cross-functionally, document results, support quality improvements and customer case resolutions, and safeguard IP for delivered technologies.

Lead design verification for SoCs, defining strategies and methodologies, and ensuring compliance and closure across various levels and components, guiding team execution and collaboration with stakeholders.

Lead RTL design and micro-architecture for ultra-dense SRAM memory compilers and SoC blocks. Implement specifications in RTL, perform synthesis and timing closure, collaborate with verification, physical design, post-silicon validation, software teams, and mentor junior engineers.

Design and develop high-performance applications integrated with embedded systems, optimizing performance and collaborating with hardware teams.

Lead functional logic verification of FPGA designs: develop verification plans, testbenches, and environments; execute simulations, debug pre-silicon issues, analyze power/timing, improve verification infrastructure, and collaborate with architects, RTL and physical design teams for coverage and integration.

Lead product engineer responsible for product development, verification expertise in memory protocols, driving product adoption, and collaborating across teams to meet customer needs.

The FPGA Silicon Design Verification Engineer performs verification of FPGA designs, develops verification plans, analyzes simulations, debugs issues, and collaborates with teams to ensure functional compliance.

Develop and execute verification plans and UVM-based testbenches to validate RISC-V CPU microarchitecture. Perform functional coverage analysis, system-level simulations, debugging, automation with scripting, and collaborate with architects and RTL designers to close verification gaps and improve verification infrastructure.

The Senior Staff Engineer will lead ASIC design processes, define standards, collaborate with teams, and mentor junior members, focusing on complex SoC architectures.

Lead the design and development of power management ICs, collaborate with cross-functional teams, and mentor junior engineers in analog IC development.

Lead verification efforts for complex IPs, develop and maintain SystemVerilog/UVM environments, drive verification closure, mentor junior engineers, and collaborate across teams.

Build and maintain FPGA prototyping platforms for ASIC designs, owning the Vivado synthesis/implementation flow, porting RTL to FPGA, closing timing on large designs, automating build scripts (TCL/Python), collaborating with design/validation teams, supporting silicon validation with FPGA images, and developing bare-metal test programs.

Lead development of next-generation mixed-signal design automation flows, collaborate with analog IC teams to deploy AI-powered tools, mentor staff, and integrate external CAE tools with ADI internal capabilities.

Design and implement DFT features (scan chains, compression, BIST), perform DFT DRC and ATPG/MBIST, validate patterns in RTL/netlist, collaborate with verification and physical design, analyze test failures, mentor junior engineers.