Top Design Engineer Jobs in Bangalore

Lead and develop complex highway design projects, ensuring safety, efficiency, compliance, and sustainability while mentoring junior engineers and managing resources.

Design and implement digital DFT for automotive power management ICs, including scan insertion, ATPG, LBIST, test-pattern validation, scan-coverage improvement, RTL coding, synthesis, timing analysis, and gate-level simulation. Collaborate with architecture, design, physical implementation, test, and silicon validation teams. Deliver and debug production test patterns, support ASIL-B/D requirements, lead design reviews, and document specifications and processes. The role requires onsite work three days per week.

Design and simulate transistor-level analog and mixed-signal IC blocks, create behavioral models, supervise physical layout, verify chip performance, support tape-out and silicon debug, collaborate with test/validation/packaging teams, and contribute to product definition and IP protection.

The Staff Design Verification Engineer leads verification strategy for complex analog and mixed-signal designs, developing environments and mentoring engineers while ensuring product quality.

Lead DFT architect responsible for improving test architecture and coverage across SoC designs. Implement and run Tessent/Modus ATPG and MBIST flows, perform scan pattern simulation, diagnosis and post-silicon bring-up, and collaborate with test engineering for pattern delivery and debug.

The Staff Design Verification Engineer leads verification strategies for complex designs, mentors junior engineers, collaborates across teams, and resolves verification challenges.

As a Staff Design Verification Engineer, lead the verification strategy for complex designs, mentor engineers, and ensure product quality through advanced methodologies.

Lead pre-silicon verification for complex SoC/subsystem designs: define verification architecture and flows, implement UVM testbenches, drive coverage closure, apply formal and power-aware (UPF) verification, coordinate emulation/FPGA/firmware teams, verify NoC/interconnects and system-level use cases, and develop scalable DV methodologies to meet quality and schedule goals.

Lead verification strategy and architecture for complex digital and mixed-signal designs. Develop UVM-based environments, drive coverage closure, debug RTL and gate-level issues, mentor engineers, coordinate cross-functional verification sign-off, and lead post-silicon validation and customer interactions.

Lead the development of verification strategies for mixed-signal designs, mentor junior engineers, and ensure product quality through sophisticated UVM-based environments.

Lead physical implementation of high-frequency CPU core blocks from RTL to GDSII. Drive synthesis, place-and-route, timing closure, CTS, and signoff. Collaborate with architecture, RTL, and power teams for aggressive PPA optimization, improve physical design flows and automation, and solve core-specific datapath and congestion challenges.

The Senior Engineer will design and develop analog circuits, focusing on power delivery applications, and execute full-chip projects, contributing to product innovation.

Design and own micro-architecture and RTL for memory sub-system modules. Collaborate with architects, verification, timing, VLSI, FPGA and software teams to implement, verify, prototype, synthesize, timing-clean, and debug designs through post-silicon bring-up.

Design and engineer low-voltage electrical control panels (MCC, PLC, VFD, HVAC, pump panels). Produce schematics, GA drawings, wiring diagrams, BOMs; perform load and cable calculations; select components; support manufacturing, FAT/SAT, commissioning, and documentation; coordinate with projects, procurement, and customers.

Design and execute offsite-built modular pump packages and plant rooms for HVAC and fire pump applications. Develop 3D models, 2D drawings, BOMs, fabrication docs, and provide technical support through project delivery, manufacturing coordination, site surveys, and commissioning while ensuring standards, quality, and design-for-manufacture practices.

Design and develop rail track alignment and related civil engineering deliverables for infrastructure projects. Produce technical drawings, calculations, and specifications; coordinate with multidisciplinary teams and clients; ensure compliance with engineering standards and support project delivery.

The Lead Design Engineer will perform design verification of ASICs, create test plans, develop functional coverage, and involve in post-silicon validation in a collaborative environment.

Seeking a Sr Principal Design Engineer with 12-14 years in VLSI, expertise in Verilog, HVL, UVM/OVM methodologies, and scripting skills.

Looking for a Sr Principal Design Engineer with 12-14 years of experience in VLSI, strong skills in Verilog and various methodologies, and expertise in test-bench development and project management.

Design and implement RTL for ASIC/FPGA front-end flow from specification to RTL/Netlist. Micro-architect and code RTL, perform lint and CDC checks, support sustenance designs, and collaborate with hardware/board engineers for system-level and board validation using company hardware design tools.

The NVM IP Platform Lead will oversee the NVM IP onboarding, release, and support processes, manage a diverse NVM IP portfolio, and mentor junior engineers.

Develop and maintain a Verification Platform for Design Verification. Collaborate with engineers to create reusable testbench components and educate teams on best practices.

Develop and maintain the Verification Platform, collaborate with engineers to create reusable testbench components, and educate teams on best practices.

Design and develop analog/RF signal chains for automotive battery management systems. Responsibilities include circuit design, simulations, and post-silicon validation.

As a Senior ASIC Design Verification Engineer, you will validate ASIC features using UVM, develop verification environments, and collaborate with teams for debugging and validation.