Top Design Engineer Jobs in Bangalore

You will manage full chip and chiplet level STA convergence, optimize the design processes, and collaborate with various engineering teams for constraints definition and implementation.

The Sr Engineer, Design Assurance role involves ensuring design compliance for medical devices, managing risk assessments, maintaining Design History Files, and supporting new product development with rigorous testing and validation processes.

This internship involves FPGA IP design and validation, supporting post-silicon system validation for next-gen Altera FPGA products, documenting specifications, and collaborating with the validation team.

The role involves leading design verification, creating test benches, simulations, and validating DSP core systems, requiring collaboration with design teams and FPGA emulation.

As a Design Verification Engineer, you will verify designs for analog and mixed signal electronics, develop verification strategies, and collaborate with teams throughout the development process.

As a Senior Design Verification Engineer, you will ensure the accuracy of designs for analog and mixed signal electronic components through analysis, testing, and software simulations.

Lead the verification of CPU designs, create and execute functional tests, collaborate with architects, and implement validation strategies. Proficient in CPU architecture and test development.

The CPU Design Verification Engineer will develop and execute verification tests, analyze simulations, debug issues, and improve CPU architectures. Collaborate with teams to enhance design quality and document plans.

As a CPU Design Verification Engineer at Intel, you will develop and execute verification tests for CPU architectures, analyze simulations, and enhance verification methodologies, ensuring high-quality product delivery.

Responsible for verifying SerDes and mixed-signal IPs, developing UVM testbenches, debugging failures across multiple layers, and collaborating with design teams.

The Principal Engineer will lead die-package co-design strategies, define package architecture, perform system-level analyses, and mentor junior engineers. The role emphasizes collaboration with various teams and customer engagement while staying current with semiconductor design trends.

The Principal Engineer will define architecture and specifications for complex SoCs, collaborate with teams, review designs, and mentor junior members.

Lead digital design of power management solutions, optimize architectures, manage design cycles, and ensure execution from architecture to tape-out.

The role focuses on verifying high-performance SoCs and involves leading verification campaigns, utilizing SystemVerilog and automation skills, and mentoring engineers. It includes power-aware and mixed-signal verification, alongside fostering collaboration across teams.

This role involves driving verification strategies for SoC designs, developing Test Plans, and collaborating with teams for verification goals in digital design and protocols.

The Design Verification Engineer will develop verification strategies, write Test Plans, and ensure SoC verification goals are met while collaborating with RTL teams and utilizing digital design skills.

Define and improve design verification processes, collaborate on test plans, debug simulation failures, and architect testbenches using UVM and C. Verify design correctness for PCIe/CXL subsystems with 18+ years of experience.

The role involves architecting and implementing simulation test benches, developing test plans, debugging simulation failures, and collaborating with logic designers for verification.

The Senior Principal Engineer will develop and implement methodologies for design automation, integrate AI in design flows, manage tools and infrastructure, and collaborate with cross-functional teams to enhance workflows and productivity.

Lead SoC-level design verification using SystemVerilog/UVM and C/assembly. Build UVM/mixed-signal testbenches, create assertions and coverage-driven tests, run regressions, and generate verification plans using vManager. Collaborate across specification, design, modeling, test, and silicon debug stages to meet project schedules.

Lead physical design closure for subsystems, collaborating with SoC teams, mentoring engineers, and improving design methodology and automation flows.

The role involves designing CMOS analog circuits, performing design reviews, conducting silicon validation, mentoring junior designers, and collaborating with various engineering teams.

The Senior Design Verification Engineer will develop verification plans, design digital blocks, support DFT implementation, mentor junior engineers, and engage in IP-level verification tasks while ensuring spec compliance and documentation quality.

As a Mixed Signal Design Verification Engineer, you will verify mixed signal logic components, develop verification plans, analyze simulations, debug issues, and collaborate with design teams.

The Design Verification Engineer performs functional verification of IP logic, develops verification plans, executes simulations, debugs issues, and maintains verification infrastructure.