Top Design Engineer Jobs in Bangalore

The Analog Circuit Design Engineer designs high-speed analog circuits, performs validations, optimizes for performance, and collaborates cross-functionally to support Intel's products.

Design and optimize high-speed SerDes PHY analog blocks, perform transistor-level design and verification, and collaborate with cross-functional teams.

The role involves RTL design and support for DDR Memory Controller IP, including design updates, customer support, and adherence to design guidelines.

Lead verification of complex CPU/SoC IP: plan verification, build constrained-random UVM/SystemVerilog or C/C++ test environments, use SVA/formal tools, debug RTL (Verilog) in simulation/emulation, develop tests and coverage, and close verification gaps to meet tape-out requirements.

Design and implement high-performance FPGA systems using Xilinx devices. Develop RTL (VHDL/Verilog), integrate reusable IP (PCIe, AXI4, DDR), write embedded firmware (C/C++) for ARM Cortex, perform system-level debug, timing closure, validation, and collaborate cross-functionally to deliver production-ready NAND flash storage solutions.

Represent systems engineering in product development for next-generation SSDs. Produce design specifications, test objectives, perform failure analysis, collaborate with ASIC/HW/firmware/validation, identify risks, and track milestones from concept through validation to meet product goals.

Lead and own complex analog IP and smaller ICs (PMICs, DC-DC, LDOs), design and compensate control loops, define block-level specs and error budgets, drive analog layout and extraction, validate silicon, mentor engineers, and manage a small team through full IC development to production while ensuring quality and schedule adherence.

Define and execute end-to-end verification strategy for SoC/testchips, develop reusable environments, VIPs and testbenches, drive coverage and formal/simulation convergence, collaborate across architecture/design/physical teams, and mentor junior engineers to achieve functional signoff and delivery quality.

Partner with hardware teams to ensure EMC compliance across design, verification, and production. Review schematics/PCB/mechanical designs, lead pre-compliance and debugging using lab instruments, diagnose EMI issues, recommend mitigations, support regulatory certification, and develop EMC guidelines to improve first-pass compliance while balancing cost, manufacturability, SI, and PI.

Design and verify complex analog/mixed-signal layouts (floorplans, power grid, ESD, bumps). Perform layout validation (DRC, antenna, density), microfloor planning, shielding/matching, and reliability checks. Collaborate with circuit, process, and package teams, develop layout methodologies, and troubleshoot layout and tool/flow issues.

The Verification Engineer designs, develops, and validates software frameworks for FPGA acceleration, collaborating with engineers to create and execute comprehensive verification strategies and test plans, utilizing various methodologies and tools.

The role involves implementation of NoC and Uncore systems, focusing on PPA optimization. Key responsibilities include leading physical design, driving co-design across levels, and mentoring junior engineers.

As a Staff Physical Design Engineer, own the physical design of memory cache structures, drive optimizations, solve bottlenecks, and improve methodologies while collaborating with cross-functional teams.

Responsible for software development related to IP blocks, defining HW/SW interfaces, collaborating with HW engineers, and ensuring efficient programmability and usability for software consumption. Involves pre-silicon validation and development of drivers and firmware prototypes.

Lead and develop verification strategies for complex analog and mixed-signal designs, mentor junior engineers, and ensure product quality.

Lead and mentor digital IP design teams to architect, implement, and deliver configurable RTL IPs. Drive IP cataloging, third-party IP evaluation, PPA and verification best practices, interface integration (DDR, PCIe, MIPI, etc.), DFT/CDC/formal flows, synthesis/STA, and cross-team alignment to accelerate SoC development.

The Staff Design Verification Engineer will lead verification strategies, mentor engineers, and solve complex verification challenges for mixed-signal designs at Analog Devices.

As an IP Design Verification Engineer, you will ensure functional correctness and reliability of IP designs, develop verification plans, simulate designs, and collaborate with various teams for efficient verification methodologies.

The Senior Staff Design Verification Engineer develops verification plans, designs digital verification flows, ensures spec compliance, conducts timing analysis, and mentors engineers while supporting the development of robust semiconductor products.

Perform block- and full-chip static (IR) and dynamic (IVD) sign-off; power estimation (vector and vectorless); signal and power EM sign-off; implement custom power grids; conduct system-level PDN analysis across board, package, interposer, and die; collaborate with SoC and packaging teams on bump assignment and package routing optimization; run vectorless, vector, and mixed-mode dynamic analyses and PG grid resistance checks.

Design and verify IO interfaces and mixed-signal blocks (POR, sensors, oscillators), develop RTL wrappers, collaborate with layout and test teams, characterize timing, support silicon validation, and produce datasheets and integration documentation.

Perform block- and full-chip static and dynamic sign-off (IR/IVD), power estimation (vector and vectorless), signal/power EM sign-off, custom power-grid implementation, PDN/system-level analysis across board/package/interposer/die, bump assignment and package routing optimization, and PG grid resistance checks.

Design and verify thermal and power management for NAND Flash (HBF-based) products. Collaborate with firmware, validation, and thermal/power designers to implement algorithms, define tests, characterize performance, and debug systems for AI infrastructure products.

Lead microarchitecture, RTL design, and delivery of UA Link Switch SoCs. Define switching and interconnect architectures, coordinate cross-functional teams, drive silicon bring-up, optimize performance/power/area, and mentor senior engineers.

Lead architecture, transistor-level design, and delivery of complex analog and mixed-signal IPs (LDOs, charge pumps, SAR ADCs, sensors, protection circuits). Drive simulation and layout-aware methodologies, silicon bring-up, production qualification, mentor engineers, and manage a small team to deliver robust power-management solutions.