Top Design Engineer Jobs in Bangalore

Design, modify, and troubleshoot complex electrical assemblies, schematics, and controllers. Perform engineering analysis and test reports, lead projects and suppliers, resolve technical issues, and produce product specifications and documentation to support semiconductor/display equipment.

The Principal Design Engineer is responsible for leading design verification projects, conducting functional verification, and developing verification environments, focusing on UVM and System Verilog.

Design and develop detailed physical layout for silicon interposers using Cadence Virtuoso. Collaborate with package technical leads and signal integrity engineers, perform feasibility studies, floorplanning, custom layout, DRC/LVS verification, and run/debug verification flows. Propose layout trade-offs, support schedules, cost, manufacturing, and electrical design issues.

Drive end-to-end physical design implementation for advanced processor IP, including synthesis, floorplanning, place and route, and signoff. Partner with architecture and RTL teams to optimize timing, power, performance, and area. Diagnose congestion, timing violations, and IR drop; contribute to methodology and automation; lead complex implementation efforts; and mentor junior engineers. The role requires advanced-node tape-out experience and expertise with Synopsys or Cadence physical design and signoff tools.

Own RTL-to-GDSII physical design implementation for high-speed System IP, including NoC fabrics, coherent CPU clusters, and memory subsystems. Develop floorplans, close timing on wide high-frequency buses, manage clock distribution, and optimize power, performance, and area on advanced process nodes. Partner with architecture and RTL teams on physical-aware design improvements, and enhance synthesis, place-and-route, sign-off, and automation methodologies.

Execute and optimize RTL-to-GDS implementation for high-performance CPU core blocks. Own block-level implementation from synthesis through GDS sign-off, drive timing, power, and area closure, use ML-based design exploration, troubleshoot implementation flows, collaborate with IP and core engineering teams, and develop Tcl/Python automation for repeatable physical design results.

Support end-to-end ASIC physical design for CPU cores, including synthesis, place and route, timing closure, RTL analysis, and PPA optimization. Automate workflows and report analysis using scripting languages, collaborate with RTL and microarchitecture teams, and develop expertise with industry-standard EDA tools while contributing to advanced RISC-V processor products.

Lead high-speed PCB design for SSD products and form factors (EDSFF, U.2), focusing on DDR/PCIe/ONFI interfaces, PDN routing with PMICs, SI/PI/EMC compliance, DFM/DFA, documentation, cross-functional collaboration, troubleshooting, and AI-assisted workflow improvements.

Design and verify analog I/O circuits (GPIOs, level shifters, LVDS, bandgaps, LDOs), run PVT and Monte Carlo simulations, perform post-layout simulations, analyze verification data, generate dotlibs/IBIS, and collaborate cross-functionally for SoC integration.

Lead system-level digital architecture and design for DSP datapaths and control blocks. Drive methodology improvements, mentor engineers, lead small technical teams, collaborate cross-functionally, engage customers, and influence product roadmaps.

Designs and troubleshoots complex mechanical systems, tooling, fixtures, layouts, and specifications. Performs engineering analyses and testing, documents results, leads projects, develops suppliers, and supports manufacturing, assembly, installation, and procurement. Applies thermodynamics, materials science, manufacturing methods, GD&T, flow analysis, and Design for Excellence principles to resolve product issues and improve cost and lifecycle performance.

Design and improve semiconductor equipment for manufacturability, assembly efficiency, quality, reliability, and supply chain robustness. Review drawings, assemblies, specifications, and BOMs; lead manufacturing-focused design reviews; support NPI, qualification, integration, ramp, and engineering changes; collaborate with suppliers on feasibility, capability, quality, and readiness; resolve deviations, non-conformances, and build issues; and drive value engineering and continuous improvement initiatives.

Design and verify mixed-signal circuits, IO interfaces, analog blocks, and digital wrappers in advanced CMOS technologies. Collaborate with layout and test engineers on physical design, characterization, silicon validation, and test-chip infrastructure. Interface with customers to define requirements and specifications, support ATE and bench testing, and produce datasheets, application notes, and integration guides.

Design and develop memory and circuit blocks at gate or transistor level for AI foundation IP. Responsibilities include circuit simulation, layout extraction, post-layout verification, physical implementation, characterization flow integration, automation scripting, memory model verification, documentation, and silicon test correlation. The role requires expertise in transistor-level behavior, device physics, signal integrity, EM/IR, reliability analysis, simulation tools, and memory circuit design, with DFT and chip integration knowledge preferred.

Designs and analyzes memory architectures and transistor-level circuit blocks, including layout, physical implementation, post-layout verification, characterization, and behavioral and physical memory models. Develops automation scripts for simulation and verification, documents specifications and timing, supports DFT and chip integration, and creates silicon test plans. The engineer also correlates silicon results with simulations and assists with silicon debug.

Design and develop high-speed memory PHYs, overseeing sub-systems and mentoring teams while ensuring quality and schedule adherence.

Lead design and execution of evaluation boards for GPUs, CPUs, and test chips. Own schematics, component selection, layout guidance, documentation, and cross-disciplinary coordination. Perform hands-on lab bring-up, validation, testing, and support production and qualification processes while ensuring platform specifications and performance targets are met.

The candidate will lead major blocks of Memory PHY layout design, perform hands-on design for critical analog and high-speed layout, and coordinate with teams for layout reviews.

Develop detailed track design plans for rail projects, perform feasibility studies, analyze alignment options, ensure compliance with standards, and provide construction support.

Lead the design and development of complex highway projects, ensuring safety, efficiency, and sustainability while managing timelines, budgets, and resources.

Lead complex digital design projects, providing technical leadership and mentoring engineers while influencing product direction and methodology improvements.

Lead RTL and microarchitecture design for Cerebras Wafer Scale Engine: author functional specs, develop RTL, synthesize, integrate third-party IP, collaborate with PD, verification and software teams, debug silicon-level functional/timing/power issues, and drive PPA and test/bring-up activities.

The role involves RTL design and support for DDR Memory Controller IP, including design updates, customer support, and adherence to design guidelines.

Verifies analog and mixed-signal semiconductor designs against design rules, procedures, specifications, and best practices. Performs equipment analysis, experimental testing, software simulations, component selection, and results evaluation to confirm device performance and reliability. Reviews vendor capabilities and collaborates with internal and external stakeholders. Requires a bachelor’s degree in electrical engineering or equivalent design experience.

Perform pre-silicon SoC design verification and emulation execution. Apply SystemVerilog and UVM, develop regression and coverage verification techniques, and validate areas including core functionality, debug fabrics, power management, security, DDR, PCIe/CXL, resets, clocks, and fuse flows. Collaborate with engineering teams while demonstrating problem-solving, communication, teamwork, and self-motivation.