Top Design Engineer Jobs in Bangalore

Lead SoC design and integration for next-generation networking DPUs and switch silicon. Define system-level methodologies, drive cross-functional SOC milestone execution, integrate subsystem pieces, and deliver models for verification across cluster/sub-system/SOC/emulation levels while collaborating with software and physical-design teams.

Design and implement SoC units by defining micro-architecture, developing RTL, collaborating with verification and physical design teams, owning silicon bring-up, and mentoring junior engineers.

Design and implement micro-architectures in RTL for memory subsystems, verify functionality, and collaborate with cross-functional teams for debugging and synthesis.

Develop and optimize mixed-signal and high-speed IPs, including RTL coding and simulation for full-chip designs, while collaborating across teams.

This role involves executing electrical engineering activities, developing diagrams, performing sizing calculations, and supporting commissioning and troubleshooting for industrial projects.

The role involves executing physical design flows, performing synthesis, floor-planning, timing closure, power optimization, and verification for ASIC/SoC blocks in audio applications.

Assist in the electrical design of electrolyzer test stations, develop schematics, support CAD modeling, and collaborate with mechanical engineers.

Lead PCIe/CXL subsystem micro-architecture, RTL implementation, integration, and sign-off. Collaborate with architecture, verification, physical design, DFT, firmware, and validation teams. Support silicon bring-up, post-silicon debug, drive coding best practices, and mentor junior designers.

Lead system-level digital architecture and design for DSP datapaths and control blocks. Drive methodology improvements, mentor engineers, lead small technical teams, collaborate cross-functionally, engage customers, and influence product roadmaps.

Design and verify analog I/O circuits (GPIOs, level shifters, LVDS, bandgaps, LDOs), run PVT and Monte Carlo simulations, perform post-layout simulations, analyze verification data, generate dotlibs/IBIS, and collaborate cross-functionally for SoC integration.

Responsible for verifying Design for Debug architecture, creating test cases and test benches using UVM. Coordinate cross-functional efforts for full coverage verification.

The Sr. SoC Design Verification Engineer is responsible for SoC architecture verification, creating test cases and test benches using UVM, coordinating efforts across teams to achieve verification goals.

The Principal Engineer will design high-performance analog/mixed-signal IP, leading implementations and collaborating across teams, while providing technical leadership and validation support.

Lead the RTL design for PCIe/CXL subsystems, collaborating with teams for architecture, validation, and integration. Mentor juniors and drive design quality improvements.

The Senior Engineer will collaborate with design teams, integrate verification processes, ensure silicon success, and assist with various tasks. Key responsibilities include problem-solving, debugging, and sharing expertise with team members.

Design and implement digital DFT (scan, ATPG, LogicBIST) for automotive PMICs, insert and validate test patterns, run gate-level simulations, improve scan coverage, reduce test time, and collaborate with architecture, P&R, test, and silicon validation teams to support tapeout and production readiness.

Responsible for full-chip and subsystem physical design (RTL-to-GDSII) for large SoCs across 40nm–3nm nodes. Tasks include floorplanning, place-and-route, CTS, timing closure, extraction, IR/EM checks, DRC/LVS, signal integrity, IP integration, methodology/flow ownership, mentoring junior engineers, and coordinating with global teams to achieve first-pass silicon.

Lead RTL and microarchitecture design for Cerebras Wafer Scale Engine: author functional specs, develop RTL, synthesize, integrate third-party IP, collaborate with PD, verification and software teams, debug silicon-level functional/timing/power issues, and drive PPA and test/bring-up activities.

Lead complex digital design projects, providing technical leadership and mentoring engineers while influencing product direction and methodology improvements.

Verify ASIC design, architecture and micro-architecture of memory subsystem IPs. Define verification scope, develop test plans, infrastructure, BFMs, monitors, checkers and scoreboards. Use coverage-driven methodologies (SystemVerilog/UVM/VMM), assertions, random stimulus, and functional coverage. Collaborate with architects, designers and pre/post-silicon teams to achieve verification closure.

Lead SoC assembly and front-end integration for Tegra chips. Own RTL quality checks, drive cross-functional execution across milestones, develop system-level methodologies, and automate flows to improve SOC implementation efficiency and correctness.

Develop detailed track design plans for rail projects, perform feasibility studies, analyze alignment options, ensure compliance with standards, and provide construction support.

Lead the design and development of complex highway projects, ensuring safety, efficiency, and sustainability while managing timelines, budgets, and resources.

The Intermediate Highway Design Engineer will develop highway geometric designs, prepare contract documents, ensure compliance with standards, and participate in design reviews and discussions.

The engineer will design and optimize high-speed analog circuits, validate designs, develop test plans, and ensure optimal layout in collaboration with teams, driving improvements for Intel's advanced products.