Principal DFT Design Engineer

Reposted 8 Days Ago
Be an Early Applicant
Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
7-7 Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
The Principal DFT Design Engineer will mentor junior engineers, lead DFT projects, use EDA tools, and drive innovation in testing methodologies.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

·     This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables.

·     Mentoring junior engineers and driving innovation/automation.

·     BE/B.Tech/M.E/M.Tech with 7+ years of relevant work experience and strong understanding of DFT concepts and good communication skills.

·     Strong hands-on experience using industry standard EDA Tools.

·     Experience with logic simulators from one or more EDA vendors.

·     Experience on industry standard ATPG tools like Cadence Modus.

·     Experience with RTL lint tools like Jasper.

·     Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required.

·     Programming in Perl/Tcl/Python or other scripting languages is a plus.

·     Experience in post silicon validation, ATE debug and support is desired.

·     Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop.

·     Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus.

·     Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 7+ years of relevant work experience
  • BE/B.Tech/M.E/M.Tech
  • strong understanding of DFT concepts
  • strong hands-on experience with EDA tools
  • experience with logic simulators
  • experience with ATPG tools
  • experience with RTL lint tools
  • experience in scan insertion and coverage analysis

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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