Top Design Engineer Jobs in Bangalore

Lead and manage VLSI design and verification teams for complex ASIC products. Own architecture, logic design, verification, simulation, physical layout coordination, program delivery, resourcing, vendor relationships, process improvement, and team development across multiple projects.

Lead verification of complex CPU subsystems and SoCs: create testbenches, test and coverage plans, develop verification environments, run constrained-random tests, collect functional coverage, debug with tools, mentor engineers, and own subsystem/IP verification flows to meet criteria.

Lead and execute SoC and CPU subsystem design verification: develop testbench architecture, test and coverage plans, implement constrained-random tests and functional coverage, debug with Verdi/Incisive, mentor verification engineers, and own verification flows and methodologies to meet IP/subsystem and full-chip verification criteria.

Lead micro-architecture and RTL development for SoC component IP (memory controllers, PCIe/CXL). Perform HW/SW co-design, timing closure, power optimization, RTL quality checks, and collaborate with architects and verification teams to deliver production-quality, timing-critical designs.

The Senior Principal Engineer will develop and implement methodologies for design automation, integrate AI in design flows, manage tools and infrastructure, and collaborate with cross-functional teams to enhance workflows and productivity.

Design, simulate, verify, characterize, and bring to production mixed-signal/analog IC blocks for hearables and wearable audio products. Collaborate with digital, software, test, and product teams; perform lab bring-up, debugging, troubleshooting, and system-level verification.

The Staff Engineer leads analog and mixed-signal block design, conducts design reviews, mentors junior engineers, and develops methodologies for advanced technology applications.

Design verification engineer responsible for mixed-signal behavioral modeling, creating verification plans/environments, SV/UVM metric-driven verification, chip-top and block-level verification, model validation, cross-discipline collaboration, and post-silicon test support to accelerate time-to-market.

Design verification engineer responsible for creating verification strategy, behavioral models for analog/mixed-signal blocks, building SV/UVM metric-driven verification environments, developing self-checking testcases, collaborating with cross-functional teams, and supporting post-silicon validation and CAD-driven DV methodology improvements.

Lead end-to-end highway and roadway drainage design tasks using Civil 3D and drainage design software. Produce detailed drawings, compute quantities, prepare design basis reports, support construction, review designs, and manage project deliverables. Work on UK projects following DMRB and international codes, and support proposals and 3D modelling.

Lead drainage design teams to deliver sustainable drainage (SuDS) schemes and hydraulic/stormwater modelling for UK projects. Produce designs, flood analyses, risk assessments, drawings and BIM/CDE deliverables using industry software, ensure QA/QMS, mentor staff, manage projects from concept to construction and support business development.

The role involves architecting and maintaining the Verification Platform build system, developing tools and build flows, and educating teams on best practices.

The job involves designing high-performance analog and mixed-signal circuits, overseeing layout engineers, performing post-silicon validation, and mentoring junior engineers with a focus on high-speed wireline and optical products.

Lead mechanical design and development of electromagnetic flow meters from concept through validation and release. Collaborate cross-functionally on material selection, manufacturability, performance, cost, and quality. Document results, support knowledge sharing, hand over technologies to manufacturing, and support quality improvements and customer case resolutions.

No role-specific responsibilities are provided. Company blurb indicates the position is a digital design engineer role at Renesas working on embedded semiconductor solutions for Automotive, Industrial, Infrastructure, and IoT.

Design and implement block, cluster, and top-level verification environments using UVM/SystemVerilog. Build testbenches and tests, drive coverage and gate-level validation, support emulation and post-silicon bring-up, debug with cross-functional teams, and lead ASIC bring-up processes to ensure silicon quality and performance.

Design and qualify system power for Cisco networking products (10W–3000W+). Develop and execute power test plans, resolve field issues, engage vendors, review schematics/BOM/layout, and perform failure/root-cause analysis and corrective actions.

Develop and execute verification strategies focused on emulation to validate complex ASIC designs. Build testbenches, run large-scale emulation tests, debug issues with designers, maintain automation and verification infrastructure, document results, and mentor junior engineers.

Lead design verification for complex ASICs: architect and build UVM/SystemVerilog DV environments, create constrained-random tests and coverage, run gate-level simulations and emulation, debug post-silicon bring-up, and manage ASIC bring-up activities across teams.

Design and qualify system power solutions for networking products (10W to 3000W+). Develop tests, execute failure/root-cause analyses, review schematics/BOMs/layouts, collaborate across hardware, ASIC, EMC, mechanical teams, and engage vendors to meet quality and regulatory requirements.

Design, develop, and verify ASIC blocks, clusters and top-level subsystems using UVM/SystemVerilog. Build and maintain DV infrastructure and testbenches, implement coverage, run gate-level simulations and emulation, support post-silicon bring-up, and lead ASIC bring-up activities with cross-functional teams.

Lead memory design validation for SRAM, multi-port, register-file, TCAM and ROM compilers in advanced process nodes. Perform functional verification, transistor-level and EM/IR analysis, signal integrity checks, Monte Carlo and timing validation, automation scripting, silicon debug and cross-team coordination to ensure accurate timing and power models.

The UX/UI Engineer will design and develop AI-enhanced interfaces, conduct user research, and collaborate with teams to create scalable, accessible experiences for AI applications.

As a Principal Design Verification Engineer, you will develop verification architectures, write test plans, and ensure design compliance across various technologies and industries.

The Principal Engineer will design critical IP, implement specifications, ensure quality, and collaborate across teams for digital IC design processes.