Principal Design Engineer

Reposted Yesterday
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
The Principal Design Engineer will manage design verification for interconnect IP, craft and execute verification plans, and collaborate with cross-functional teams.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

  • Design Verification for interconnect IP
  • Relevant experience in interconnect and subsystems is strongly preferred
  • Crafting verification plans and executing on those plans to verify highly complex and configurable designs.
  • Responsible for coverage collection and closure
  • Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Required Skills and Experience:

  • 8+ years of design verification experience
  • BS (or higher) in EE/Computer Engineering
  • Strong technical and interpersonal skills
  • Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
  • Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
  • Experience with development of fully automated flows
  • Exposure to scripting languages like Perl, Unix shell or similar languages
  • Experience with Formal Verification will be a plus
  • Experience with Gate Level Simulations
  • Excellent written and oral communication skills necessary
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 8+ years of design verification experience
  • BS (or higher) in EE/Computer Engineering
  • Excellent knowledge of Interconnects, NoCs and design verification fundamentals
  • Strong technical and interpersonal skills
  • Thorough understanding of System Verilog, UVM, and other programming languages
  • Experience with development of fully automated flows
  • Exposure to scripting languages like Perl, Unix shell or similar languages
  • Experience with Formal Verification
  • Experience with Gate Level Simulations

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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