Top Design Engineer Jobs in Bangalore

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

Design, layout, and optimize memory/logic/analog circuits; perform parasitic modeling, simulation and verification; manage floor-planning, placement, routing and tape-out validation; coordinate cross-functional manufacturability and drive memory-generation innovation while leveraging AI-based tools to improve workflow.

Lead FPGA design from concept to production, mentor team, manage risks, define methodologies, and ensure quality in compliance with industry standards.

As a Silicon Logical Design Engineer, you will produce high-quality microarchitecture and RTL, collaborate across teams, and help ensure successful chip delivery.

The role involves designing and implementing high-speed RTL blocks, ensuring robustness against various factors, integrating and debugging RTL, and collaborating on verification and timing closure support.

Seeking skilled silicon physical design engineers to develop AI superchips, utilizing advanced technologies, enhancing design flows, and problem-solving collaboratively.

Lead technical aspects of electromechanical product design, develop concepts, mentor engineers, and resolve complex issues in aerospace projects.

Design, implement, and optimize FPGA-based Radio and RAN Compute solutions. Integrate FPGA designs with hardware and software, apply industry-standard tools and HDLs, document specifications and test results, participate in design reviews, and research FPGA and ML/AI advancements to improve performance, power, and cost efficiency.

The role involves ownership and design of analog sub-blocks in high-speed PHYs, mentoring junior engineers, and collaborating on complex circuit designs.

As a Senior Engineer in ASIC Design, you'll develop and document ASIC IP blocks, optimize design methodologies, and collaborate on cutting-edge 5G and 6G technologies.

Design and implement complex analog circuits for advanced DRAM products, oversee layout processes, validate designs, and mentor junior engineers. Collaborate across multiple teams to enhance product manufacturability using AI tools.

As a Memory Mask Design Engineer at NVIDIA, you'll implement high-performance CMOS integrated circuit layouts, specifically for digital memory, while using advanced EDA tools and following industry standards.

The Physical Design Engineer will perform synthesis, timing closure, and integration tasks, collaborating with the RTL team to optimize design flow.

Lead and execute physical design activities for semiconductor blocks: floorplanning, placement, clock-tree synthesis, routing, timing closure, power optimization, and signoff. Collaborate with RTL, timing, and verification teams, drive timing convergence, resolve DRC/LVS issues, and mentor junior engineers to deliver tapeout-ready layouts.

Develop and maintain CAD/Revit tools and templates to automate repetitive tasks, ensure data flow across teams, support low-voltage security system design, deliver training and documentation, manage client onboarding, and maintain design quality and standards.

Design and own RTL micro‑architecture for digital control blocks in high‑speed mixed‑signal PHYs. Define digital/analog interfaces, implement calibration algorithms, ensure protocol/IP compliance (PIPE), drive front‑end closure (lint/CDC/formal/STA), collaborate with AMS and DV teams, and support post‑silicon bring‑up and debug.

Lead PCIe/CXL subsystem microarchitecture, RTL implementation and integration. Collaborate with architecture, verification, physical design, DFT, firmware and validation teams. Support silicon bring-up and post-silicon debug, drive design quality and reuse, and mentor junior designers.

Perform structural analysis and design of water/sewage treatment and non-plant steel and concrete structures to Eurocodes. Build analytical models using Robot, STAAD, IDEA StatiCa; prepare calculations, reports, loads and stresses under senior supervision. Provide design input to CAD/BIM, coordinate drawings, and ensure compliance with Arcadis systems and H&S regulations.

Lead micro-architecture and RTL development for memory-subsystem interconnect IP. Implement, verify, and deliver synthesis- and timing-clean designs. Collaborate with architects, verification, timing/VLSI/physical teams, FPGA and software teams for prototyping, and perform post-silicon bring-up and debug.

Lead early GPU floorplanning and SOC planning, collaborating with architects and physical design teams to optimize area, timing, congestion, power/clock distribution, packaging and P&R. Perform feasibility studies, influence early implementation decisions, drive area reviews, and build tools/infrastructure to improve chip area and execution speed.

Lead design and development of high-speed memory IP (GDDR7/DDR5/LPDDR6). Perform analog design, layout, digital integration, documentation, silicon validation, and customer-facing discussions throughout full IP lifecycle from specification to silicon characterization.

Design, develop, and modify mechanical layouts, tooling, fixtures, and assemblies. Perform engineering analysis, testing, documentation, and troubleshooting. Coordinate procurement, assembly, and installation of mechanical components while ensuring manufacturing and industry standards compliance.

Design and deliver RTL for mixed-signal DDR PHY IPs using SystemVerilog; define architecture/microarchitecture, implement RTL, set up front-end automation and tool flows (lint, CDC, RDC, synthesis), ensure RTL quality, optimize area/power with UPF/clock gating, and collaborate with validation, backend, and SoC teams while driving tooling and methodology improvements.

Design and own micro-architecture and RTL for memory subsystem / interconnect IP, implement synthesis/timing-clean RTL, collaborate with architects, verification, timing/VLSI, FPGA/SW prototyping, and perform post-silicon debug.

Lead and execute IC package design from concept through implementation. Optimize pinouts, stack-ups, PDN, and high-speed routing. Collaborate with silicon floorplanning, SI/PI, and layout teams, improve methodologies, mentor engineers, and work with vendors on multi-die and interposer solutions for high-performance ASICs.