Top Design Engineer Jobs in Bangalore

Design and develop custom digital DFT circuits, implement testability features, collaborate with engineers, and perform circuit simulations to enhance memory testability.

The DFT Design Engineer will design custom digital DFT circuits, define testability features, and perform simulations, collaborating with other designers and product engineering.

As a Silicon Logical Design Engineer, you will produce high-quality microarchitecture and RTL, collaborate across teams, and help ensure successful chip delivery.

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

The Staff ASIC Physical Design Engineer will develop block-level physical design for ASICs, focusing on low power implementation, timing closure, and physical verification. Required skills include expertise with Cadence tools and advanced process technologies, alongside strong analytical and interpersonal abilities.

The Staff Engineer will lead ASIC verification, creating test plans, developing UVM environments, and ensuring silicon success while mentoring junior engineers.

Design, implement, and integrate complex analog circuits for advanced DRAM products, managing layouts, verification, and mentoring junior designers while collaborating across groups.

The role involves IP/Block/Subsystem verification, test plan creation, UVM testbench development, and mentoring junior engineers.

The role involves designing and optimizing analog circuits, managing layout processes, and collaborating with various teams for product manufacturability. It includes mentoring junior engineers and contributing to innovation in memory technology.

Seeking skilled silicon physical design engineers to develop AI superchips, utilizing advanced technologies, enhancing design flows, and problem-solving collaboratively.

Lead mechanical design and tooling projects from concept to implementation. Use UG/NX and CAD to create layouts, drawings, and specifications; perform engineering analyses; design custom tooling and fixtures; drive process improvements; develop test plans and documentation; and collaborate with suppliers and cross-functional teams to deliver manufacturable mechanical solutions.

You will implement, synthesize, and achieve timing and performance goals while collaborating on architecture and providing mentorship.

Lead CPU microarchitecture and RTL development to deliver high-performance, low-power CPU cores. Define microarchitecture, specify features, guide RTL implementation and verification, and collaborate with cross-functional teams on timing, power, area, and SoC integration.

The Staff Engineer will focus on RTL design, SoC integration, and collaborate with cross-functional teams while leveraging AI skills.

As a Design Engineer II, you'll lead silicon subsystem prototyping and validation, manage hardware design, and debug SERDES technologies while mentoring junior engineers.

The GPU SOC Design Engineer develops logic design and RTL coding for graphics IPs, participates in architecture definition, optimizes design, and ensures verification of features.

The DFT Design Engineer will develop and implement DFT methodologies, optimize designs, support manufacturing testing, and collaborate with teams to ensure high-quality silicon products.

As a DFT Design Engineer, you will develop DFT features, support timing closure, generate test content, and collaborate on architecture for silicon products.

The role involves leading VLSI design engineering, overseeing project schedules, and developing complex test benches and verification methodologies.

The Physical Design Engineer will lead the design of Client SoCs, performing implementation, optimization, verification, and collaboration with teams to enhance semiconductor technology.

The role involves executing SoC physical design implementations, ensuring high-quality designs, performing analysis, and optimizing methodologies for efficiency in a fast-paced team environment.

As a DFT Design Engineer, you will enhance test coverage and manufacturability, developing DFT architectures and working with cross-functional teams to ensure testing of silicon solutions.

The role involves physical design implementation, static timing analysis, power domain analysis, and collaborating with teams to optimize SoC designs.

Lead DFT ownership across projects: define test architecture, implement RTL DFT changes, perform scan insertion/LEC/CLP checks, develop test-mode timing constraints, run ATPG and timing simulations, implement/verify boundary-scan, ACJTAG, IEEE1500 and IEEE1687 (iJTAG) ICL/PDL, support post-silicon bring-up, and interact with customers and pre-sales.

Lead and execute functional verification for complex VLSI designs using SystemVerilog and UVM. Plan environments, generate test plans, develop verification environments, drive projects from concept to verification closure, and mentor teams. Prior memory IP (DDR/HBM/GDDR) verification experience is a plus.