Top Design Engineer Jobs in Bangalore

Design and deliver signoff-quality silicon layouts for leading-edge AI chips using state-of-the-art EDA tools and in-house flows. Responsibilities include floorplanning, synthesis, place-and-route, timing closure, physical verification, flow/tool enhancement, debugging complex issues, and cross-team collaboration with architecture, packaging, and foundry partners.

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

Deliver microarchitecture and RTL for Graphcore silicon: integrate IP/subsystems into SoC, maintain build/config environments, run synthesis/lint/CDC/timing checks, support verification and physical design handoffs, debug integration issues, improve automation and integration flows, and produce high-quality documentation.

Lead die- and block-level physical implementation for advanced-node SoCs: floorplanning, full-chip place-and-route, PDN design, CTS, timing-driven closure, physical verification to GDSII, and develop/maintain PnR automation (Tcl/Python). Collaborate with RTL, synthesis, DFT, STA and package teams and support synthesis/STA sign-off using Fusion Compiler and PrimeTime.

Design and validate advanced analog mixed-signal circuits for HBM products including amplifiers, comparators, bandgap refs, LDOs, charge pumps, oscillators, DLLs and IOs (DDR/LPDDR). Drive layout, EM/IR optimization, parasitic modeling, tape-out revisions, reliability verification, and cross-functional integration with power delivery, process, test, and product teams. Use industry simulators and AI tools to improve PPA and delivery.

Design and integrate complex analog circuits (amplifiers, comparators, bandgaps, LDOs, charge pumps, oscillators, DLLs, IOs, sensors), develop custom digital blocks, perform parasitic modeling and simulation, manage layout and tape-out, collaborate cross-functionally for manufacturability, mentor junior designers, and apply agentic AI tools to improve PPA and delivery.

Lead ASIC physical design for enterprise SSD processors/controllers including floorplanning, placement, CTS, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC, tape-out. Drive APR flow development, PPA analysis, advanced-node (5nm/3nm) implementation, Redhawk-SC/Innovus/Tempus/Calibre tool usage, and manage subsystem team deliverables.

Lead design, implementation, and integration of complex analog circuits and custom digital blocks for advanced DRAM products. Perform parasitic modeling, verification with industry simulators, oversee layout/floorplanning and tape-out revisions, collaborate across manufacturing and product teams, mentor junior designers, and apply agentic AI (e.g., Claude) to improve PPA and delivery.

Design, implement, and integrate complex analog circuits and custom digital blocks for advanced DRAM products. Perform parasitic modeling, simulation, layout oversight (floor-planning, placement, routing), tape-out activities, cross-functional coordination, and mentor junior designers. Leverage AI tools and agentic models (e.g., Claude) to improve engineering efficiency and PPA.

Design, implement, and integrate complex analog circuits and custom digital blocks for advanced DRAM/HBM products. Perform parasitic modeling, verification with industry simulators, oversee layout (floor-planning, placement, routing), and ensure manufacturability through cross-functional collaboration. Mentor junior designers and apply strong AI skills (agentic models, tools like Claude) to improve PPA and delivery.

Lead analog design efforts for high-speed PHY sub-blocks at advanced process nodes (12nm and below). Own specifications and implementation, collaborate with a skilled analog team, and leverage AI-assisted design workflows where applicable.

Supports pre-sales engineering for global fire detection system projects. Reviews specifications and MEP drawings, develops bills of material, selects hardware and software, performs cable calculations, prepares cost estimates and technical documentation, and participates in project reviews. Ensures quality, schedule adherence, customer satisfaction, escalation management, reporting, and compliance with applicable fire detection standards. Provides coaching to team members and supports technical sales capabilities.

Designs high-voltage, high-power electronics for electric vehicle energy-management systems, including chargers, converters, battery-management systems, and motor controllers. Responsibilities include requirements definition, schematic and PCB design, circuit and thermal analysis, component qualification, board bring-up, validation, EMC troubleshooting, hardware debugging, and functional-safety documentation supporting ISO 26262 compliance.

Designs, simulates, verifies, and tests VLSI components and ASIC architectures for computer and server systems. Develops algorithms, evaluates circuit performance, and supports prototype or production solutions while meeting quality, schedule, and cost targets. Collaborates with internal teams and outsourced development partners, communicates project status, resolves issues, and mentors less experienced engineers.

Develop and integrate RTL logic designs into complex SoC architectures. Perform simulation, quality checks, and corrective actions to meet power, performance, timing, and area targets. Collaborate with IP providers to validate SoC-level integrations, review verification plans, resolve failing RTL tests, and optimize designs using advanced methodologies and tools.

The role involves IC layout design for high-performance memory circuits, leading layout architecture, verification, and mentoring junior engineers while optimizing design methodologies.

Participate in TI’s 12-month Career Accelerator Program as a Digital IC Design Engineer. Design, model, implement, verify, and document digital circuits and advanced processor systems while balancing performance, power, cost, and schedule. Responsibilities include architecture trade-off analysis, design reviews, IC layout supervision, prototype characterization, test specification development, product release coordination, and behavioral modeling. The role targets new college graduates with an electrical or computer engineering background and a minimum 3.0 GPA.

Lead physical design implementation and integration at block/subsystem/sub-chip/SoC levels including floorplanning, synthesis, placement, CTS, routing, STA, physical verification, formal equivalency, power integrity (IR-drop/EM) and tapeout readiness. Drive PD flow automation, team delivery against milestones, vendor/IP evaluations, and report progress, issues, and risks to management.

Design and verify advanced analog and mixed-signal circuits (PLLs, LC oscillators, clocking) in advanced process nodes. Extract chip parameters, create test plans, optimize for power/performance/area/timing/yield, collaborate with architecture and layout teams, and use transistor-level simulation and solver tools for inductor characterization and post-layout verification.

Design and deliver mixed-signal DDR PHY logic: define architecture, implement RTL in SystemVerilog, ensure RTL quality using frontend tools (lint/CDC/RDC/synthesis), drive low-power and area optimizations, create FE packages and automation flows, and collaborate across validation, backend, and SoC teams.

Perform full-custom analog/mixed-signal IC layout in advanced foundry nodes (2nm-7nm+); own physical verification (DRC/LVS/density/tape-out checks); resolve complex layout issues; optimize for performance, area and manufacturability; mentor junior engineers; collaborate cross-functionally and represent the team in technical discussions.

Design and implement microarchitecture and RTL for mixed-signal/high-speed IP using SystemVerilog. Collaborate with architecture and SoC teams to optimize power, performance, and area; run lint/CDC/synthesis checks; perform power/performance analysis; support verification, integration, and automation to improve coverage and timing convergence.

Design and optimize FPGA-based NAND Flash storage systems using Xilinx architectures and VHDL/Verilog RTL. Develop reusable IP cores, PCIe, AXI4, DDR, and serial interfaces; build embedded firmware and device drivers for Zynq SoCs; and lead validation, verification, timing closure, signal integrity, and hardware-software debugging. Mentor engineers, contribute to architectural decisions, document designs, and collaborate with cross-functional teams and stakeholders.

Design and integrate complex analog and custom digital blocks for advanced DRAM (HBM) products, perform parasitic modeling, validation, and tape-out revisions; oversee layout (floor-planning, placement, routing), run simulations with industry simulators, collaborate across functions for manufacturability, mentor junior designers, and apply AI/agentic AI tools (e.g., Claude) to optimize PPA and delivery.

Design and optimize high-speed SERDES PHY, analog, and mixed-signal IC layouts. Collaborate with design and physical design teams on block PnR, debug DRC, ERC, LVS, EMIR, and PERC issues, and resolve signal integrity, ESD, latch-up, parasitic, reliability, and PPA challenges. Conduct layout reviews, provide technical feedback, and improve layout methodologies for advanced CMOS and FinFET processes.