Top Design Engineer Jobs in Bangalore

As a Silicon Logical Design Engineer, you will produce high-quality microarchitecture and RTL, collaborate across teams, and help ensure successful chip delivery.

The role involves designing and implementing high-speed RTL blocks, ensuring robustness against various factors, integrating and debugging RTL, and collaborating on verification and timing closure support.

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

Design, implement, and optimize FPGA-based Radio and RAN Compute solutions. Integrate FPGA designs with hardware and software, apply industry-standard tools and HDLs, document specifications and test results, participate in design reviews, and research FPGA and ML/AI advancements to improve performance, power, and cost efficiency.

The Principal Design Engineer is responsible for leading design verification projects, conducting functional verification, and developing verification environments, focusing on UVM and System Verilog.

Design and develop custom digital DFT circuits, implement testability features, collaborate with engineers, and perform circuit simulations to enhance memory testability.

Design and verify analog I/O circuits (GPIOs, level shifters, LVDS, bandgaps, LDOs), run PVT and Monte Carlo simulations, perform post-layout simulations, analyze verification data, generate dotlibs/IBIS, and collaborate cross-functionally for SoC integration.

Lead and own complex analog IPs and subsystems for power products (PMICs, DC-DC converters, LDOs). Design and compensate control loops, perform block-level spec breakdown and error budgeting, drive layout collaboration and simulation/extraction flows, debug silicon, mentor engineers, and manage a small team through end-to-end IC development to production while defining I/O protection and reliability.

The candidate will lead major blocks of Memory PHY layout design, perform hands-on design for critical analog and high-speed layout, and coordinate with teams for layout reviews.

Lead RTL and microarchitecture design for Cerebras Wafer Scale Engine: author functional specs, develop RTL, synthesize, integrate third-party IP, collaborate with PD, verification and software teams, debug silicon-level functional/timing/power issues, and drive PPA and test/bring-up activities.

Lead complex digital design projects, providing technical leadership and mentoring engineers while influencing product direction and methodology improvements.

Design and develop high-speed memory PHYs, overseeing sub-systems and mentoring teams while ensuring quality and schedule adherence.

Design and deliver high-speed DDR IO solutions for next-generation memory in advanced CMOS nodes. Tasks include IO block design, powerbus analysis, jitter/timing closure, collaboration with layout and verification teams, and proposing innovative design methodologies.

Lead SoC assembly and front-end integration for Tegra chips. Own RTL quality checks, drive cross-functional execution across milestones, develop system-level methodologies, and automate flows to improve SOC implementation efficiency and correctness.

Lead full-chip integration including die architecture, die size estimation, floorplan and module placement. Design and implement full-chip power distribution and floorplanning to minimize parasitics and die size. Collaborate with multi-site design and process engineering teams, manage small teams, and drive layout automation and verification strategies to achieve sign-off.

Develop and validate SystemC/C++ functional models and tests, debug firmware and testbench failures (SystemC/SV/UVM), root-cause issues with cross-team collaboration, and mentor junior engineers.

As a Principal DevSecOps Engineer at Zscaler, you will lead the integration of security in DevOps processes, mentor teams, and enhance cloud security strategies, focusing on continuous improvement and vulnerability management.

Develop detailed track design plans for rail projects, perform feasibility studies, analyze alignment options, ensure compliance with standards, and provide construction support.

Lead the design and development of complex highway projects, ensuring safety, efficiency, and sustainability while managing timelines, budgets, and resources.

The Intermediate Highway Design Engineer will develop highway geometric designs, prepare contract documents, ensure compliance with standards, and participate in design reviews and discussions.

The engineer will design and optimize high-speed analog circuits, validate designs, develop test plans, and ensure optimal layout in collaboration with teams, driving improvements for Intel's advanced products.

The Analog Circuit Design Engineer at Intel focuses on designing, developing, and optimizing high-speed analog circuits, collaborating with cross-functional teams and contributing to post-silicon debug efforts.

The Analog Circuit Design Engineer designs high-speed analog circuits, performs validations, optimizes for performance, and collaborates cross-functionally to support Intel's products.

Design and develop high-speed analog circuits, optimize designs for performance and power efficiency, validate circuits, and collaborate with teams.

Design and optimize high-speed SerDes PHY analog blocks, perform transistor-level design and verification, and collaborate with cross-functional teams.