Top Design Engineer Jobs in Bangalore

As a Silicon Logical Design Engineer, you will produce high-quality microarchitecture and RTL, collaborate across teams, and help ensure successful chip delivery.

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

The Staff ASIC Physical Design Engineer will develop block-level physical design for ASICs, focusing on low power implementation, timing closure, and physical verification. Required skills include expertise with Cadence tools and advanced process technologies, alongside strong analytical and interpersonal abilities.

Seeking skilled silicon physical design engineers to develop AI superchips, utilizing advanced technologies, enhancing design flows, and problem-solving collaboratively.

The DFT Design Engineer will design custom digital DFT circuits, define testability features, and perform simulations, collaborating with other designers and product engineering.

Design and develop custom digital DFT circuits, implement testability features, collaborate with engineers, and perform circuit simulations to enhance memory testability.

The Staff Engineer will focus on RTL design, SoC integration, and collaborate with cross-functional teams while leveraging AI skills.

The role involves designing and optimizing analog circuits, managing layout processes, and collaborating with various teams for product manufacturability. It includes mentoring junior engineers and contributing to innovation in memory technology.

The Physical Design Engineer will lead the design of Client SoCs, performing implementation, optimization, verification, and collaboration with teams to enhance semiconductor technology.

The role involves executing SoC physical design implementations, ensuring high-quality designs, performing analysis, and optimizing methodologies for efficiency in a fast-paced team environment.

As a DFT Design Engineer, you will enhance test coverage and manufacturability, developing DFT architectures and working with cross-functional teams to ensure testing of silicon solutions.

The role involves physical design implementation, static timing analysis, power domain analysis, and collaborating with teams to optimize SoC designs.

Lead DFT ownership across projects: define test architecture, implement RTL DFT changes, perform scan insertion/LEC/CLP checks, develop test-mode timing constraints, run ATPG and timing simulations, implement/verify boundary-scan, ACJTAG, IEEE1500 and IEEE1687 (iJTAG) ICL/PDL, support post-silicon bring-up, and interact with customers and pre-sales.

Lead and execute functional verification for complex VLSI designs using SystemVerilog and UVM. Plan environments, generate test plans, develop verification environments, drive projects from concept to verification closure, and mentor teams. Prior memory IP (DDR/HBM/GDDR) verification experience is a plus.

Lead design verification efforts using SystemVerilog and UVM: plan verification environments and test plans, develop functional verification environments, verify complex designs, and drive projects to verification closure. Memory IP (DDR/HBM/GDDR) experience is a plus.

The Lead Design Engineer will code in RTL, create datapath designs, and manage complex FIFO design while collaborating with analog design teams.

Lead hardware engineer for product design, developing specifications, schematics, and layouts, collaborating with teams, performing validations, and transitioning to production.

Design and implement complex analog circuits for advanced DRAM products, oversee layout processes, validate designs, and mentor junior engineers. Collaborate across multiple teams to enhance product manufacturability using AI tools.

Manage a team to deliver effective engineering designs for robotic automation systems, ensuring high quality and timely solutions. Collaborate across teams, manage design plans, and support customer interaction during project execution.

As a Mechanical Design Engineer, you'll solve mechanical problems, design tooling, oversee manufacturing processes, and ensure adherence to industry standards while developing specifications and coordinating projects.

Designs complex layouts of analog signal circuits, runs design verification tools, develops layout methodologies, and collaborates with teams to meet specifications.

Lead design and integration of analog/power IP blocks for PMICs, including regulators, charge pumps, oscillators, ADCs, and protection circuitry. Drive control-loop design, analog/FET layout guidance, simulation/extraction flows, and take ownership from design through silicon verification.

The IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in FPGA's, develop analog circuits for IO applications, work with design requirements, optimize circuits, and support post-tapeout phase.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.

Design and develop analog and mixed-signal circuits for embedded Flash Memory, collaborating with teams to optimize performance and reliability while mitigating risks.