Top Design Engineer Jobs in Bangalore

As a Design Engineer, you will build and maintain the documentation platform, collaborate with teams to improve customer experiences, and implement feedback improvements.

The E-Motor Design Engineer specializes in designing and developing electric motors for automotive applications, ensuring compliance with standards and optimizing methodologies.

Design and develop high-speed memory PHYs, overseeing sub-systems and mentoring teams while ensuring quality and schedule adherence.

The Engineer Gearbox Design will conduct tolerance studies using 1D and 3D analysis methods, interpret results, and document findings while improving tolerance situations.

The Principal Design Engineer is responsible for leading design verification projects, conducting functional verification, and developing verification environments, focusing on UVM and System Verilog.

Design and optimize sheet metal components and thermal systems for the e^pump with a focus on manufacturability and performance requirements.

The Verification Engineer will handle pre-silicon verification of IP modules, defining verification plans, and collaborating with hardware and software design teams. Responsibilities include UVM development, test case design, simulation debugging, and coverage analysis.

Cerebras Systems seeks a skilled Physical Design Engineer. Responsibilities include physical design tasks, integration with RTL teams, optimizing power/performance/area, and using verification methodologies and tools.

Looking for silicon physical design engineers to develop AI superchips, focusing on high-performance designs and working with multiple teams to enhance design flows and solve complex engineering problems.

The Analog Digital Mask Design Engineer will execute high-performance IC layout for CMOS integrated circuits, optimize designs, and verify layouts while following industry standards.

The intern will assist in designing metal and composite parts for aircraft, develop CATIA macros, create CAD models, and collaborate with teams to meet design requirements.

The candidate will lead major blocks of Memory PHY layout design, perform hands-on design for critical analog and high-speed layout, and coordinate with teams for layout reviews.

Responsible for micro-architecture and RTL development of design modules, analyzing system implications, and collaborating with teams to ensure design meets requirements.

Design and develop RTL for ASIC memory subsystems, collaborating with teams for verification, synthesis, and debugging, while making architectural decisions.

Lead the design and development of robotic automation systems for BIW applications, ensuring compliance with standards and coordinating with teams.

Lead various engineering projects, focusing on dry utility network design, client relationships, and managing design documentation for electrical engineering tasks.

Design and develop SRAM circuits, supervise layout implementation, and collaborate with teams for SOC design and silicon testing.

The role involves SRAM design, compiler development, and collaboration with SOC design teams to achieve optimal performance for silicon products.

Lead HV and EHV substation design projects, including creating deliverables, design calculations, client communication, and mentoring juniors. Ensure quality and interdisciplinary coordination.

The role involves micro-architecture and RTL development for memory subsystem components, collaboration with various teams, and post-silicon verification.

Lead all block/chip level physical design activities for GPUs and ASICs. Improve RTL2GDS flow, debug design issues, and collaborate with design teams.

As a Staff Design Engineer specializing in Android, you will build UI components, collaborate with teams, and ensure design and engineering alignment.

The Senior Design Engineer will build Android UI components, collaborate on design systems, and maintain stable user experiences while supporting product teams.

Design, simulate, and verify custom CMOS memory blocks. Collaborate with design teams on projects and ensure quality for memory IP release.

Responsible for the end-to-end development of IO IPs, collaborating on design architecture, circuit design, and supervising layout engineers.