Top Design Engineer Jobs in Bangalore

Seeking skilled silicon physical design engineers to develop AI superchips, utilizing advanced technologies, enhancing design flows, and problem-solving collaboratively.

The Staff ASIC Physical Design Engineer will handle physical design implementation, including floorplanning, placement, routing, and timing closure for ASICs, focusing on low power designs and advanced technologies.

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

Lead FPGA design from concept to production, mentor team, manage risks, define methodologies, and ensure quality in compliance with industry standards.

As a Silicon Logical Design Engineer, you will produce high-quality microarchitecture and RTL, collaborate across teams, and help ensure successful chip delivery.

The role involves designing and implementing high-speed RTL blocks, ensuring robustness against various factors, integrating and debugging RTL, and collaborating on verification and timing closure support.

Design and develop ASIC IP blocks and subsystems for 5G/6G, perform RTL sign-off and documentation, collaborate with architects and verification engineers, optimize design methodologies, and contribute across teams to deliver projects.

The staff engineer will work on ASIC physical design including floorplanning, routing, timing closure, and physical verification, with a focus on enterprise SSD design.

The role involves designing and optimizing analog circuits, managing layout processes, and collaborating with various teams for product manufacturability. It includes mentoring junior engineers and contributing to innovation in memory technology.

Lead a team of design engineers in delivering high-impact ASIC IP solutions, overseeing project alignment, and fostering innovation and cross-team collaboration.

The role involves micro-architecture and RTL development for memory subsystems, collaborating with various teams to ensure performance and correctness, and handling post-silicon verification.

Responsible for micro-architecture and RTL development for High Speed IO IPs, ensuring performance, power, and area requirements are met while collaborating with various teams for verification and validation.

As an ASIC Design Engineer, you will implement BOOT and power management architecture, micro-architecture design, RTL development, and collaborate with cross-functional teams to verify chip correctness.

The role involves overseeing mixed signal IP logic design, improving power/area metrics, and collaborating with cross-functional teams. Responsibilities include RTL design, automation of design flows, and ensuring quality through front-end tools.

The role involves overseeing engineering assignments for substation projects, ensuring adherence to safety, quality, and budget requirements. Responsibilities include evaluating engineering techniques, providing technical support, collaborating with suppliers, and coordinating tasks for entry-level engineers.

Lead RTL development and microarchitecture for a high-performance, low-power AI CPU core. Define architecture, implement RTL, support functional verification, and collaborate with cross-functional teams to meet power, performance, area, timing, reliability, and test goals.

Lead the design and development of electromechanical products, resolve complex engineering issues, and provide technical guidance within cross-functional teams.

Design and execute advanced semiconductor package layouts (2.5D/3D, FCBGA, SiP, chiplets), maintain CAD databases, generate manufacturing outputs, ensure DRC/LVS compliance, and collaborate with SI/PI, thermal, reliability, and manufacturing teams throughout ECO cycles.

Lead mechanical design and tooling projects from concept to implementation. Use UG/NX and CAD to create layouts, drawings, and specifications; perform engineering analyses; design custom tooling and fixtures; drive process improvements; develop test plans and documentation; and collaborate with suppliers and cross-functional teams to deliver manufacturable mechanical solutions.

Design, develop, and verify Soft IP: translate microarchitectural specs into RTL (SystemVerilog), run IP qualification flows, create timing collateral and waivers, support SoC integration, automate tasks with Perl/Python, document results and collaborate cross-functionally.

Design and validate analog circuits and custom layouts from micro-architectural specs for HIP/SoC integration. Develop timing collateral, perform analog validation and debugging, support Soft IP deployment, and collaborate with multidisciplinary teams to meet delivery standards.

The Analog Design Engineer will design analog blocks for DAC products, requiring experience with various analog IPs and tools like Cadence Virtuoso.

Lead an Analog IC design team, manage projects from definition to release, collaborate with various teams, and ensure customer needs are met.

Lead the design and verification of analog and mixed-signal circuits for embedded Flash Memory IPs, ensuring optimal performance and reliability.

The Digital Design Engineer will develop mixed-signal devices for audio applications, focusing on digital logic circuits, RTL design, and collaboration with cross-functional teams.