Top Design Engineer Jobs in Bangalore

Develops physical designs for next-generation AI semiconductors, delivering signoff-quality chip layouts at advanced process nodes. Responsibilities include floorplanning, synthesis, placement and routing, clock-tree synthesis, timing analysis, logical equivalence, physical verification, flow enhancement, scripting, debugging, and PPA optimization. The engineer collaborates with RTL, verification, DFT, architecture, packaging, product engineering, foundries, and external support teams.

Design and develop mechanical and electrical solutions for automated and special test equipment used in aerospace testing. Responsibilities include rack, wiring, harness, schematic, and layout design; CAD and PLM documentation; connector and measurement equipment selection; qualification and verification testing; troubleshooting; obsolescence management; failure investigations; and test-plan development. The engineer will coordinate with technical leads, customers, and global teams while managing test-program scope, cost, schedules, integration, documentation, and deployment.

Design and develop special and automated test equipment for aerospace products at circuit-card, LRU, and system levels. Responsibilities include electrical architecture, schematics, PCB, rack wiring and harness design; equipment and sensor selection; troubleshooting; obsolescence management; system integration; qualification testing; and technical documentation. The engineer will coordinate with technical leads and customers, lead failure investigations, manage test-program scope, cost, and schedule, and support prototype, verification, and formal testing.

Integrate IP and subsystems into top-level SoC designs, develop RTL and microarchitecture, maintain build environments, and perform synthesis, linting, CDC/RDC, and timing checks. Support verification and physical design teams through interface handoffs, debug integration issues, improve automation flows, produce documentation, and coordinate consistent practices across sites.

Lead analog/mixed-signal circuit design for HBM products: design, simulate (HSPICE/FINESIM/Verilog), optimize layout and EM/IR, validate reliability, manage tape-outs and layout flows, integrate with PDN, mentor teams, and apply AI tools to improve PPA and delivery.

Design and deliver signoff-quality silicon layouts for leading-edge AI chips using state-of-the-art EDA tools and in-house flows. Responsibilities include floorplanning, synthesis, place-and-route, timing closure, physical verification, flow/tool enhancement, debugging complex issues, and cross-team collaboration with architecture, packaging, and foundry partners.

Design and validate complex analog mixed-signal circuits for advanced HBM products including amplifiers, comparators, references, IO (DDR/LPDDR), charge pumps, oscillators, DLLs, and sensors. Lead layout, floor-planning, placement, routing and EM/IR optimization. Perform simulations with FINESIM/HSPICE/Verilog, parasitic modeling, reliability/degradation verification, tape-out support, and cross-functional collaboration. Provide technical leadership, standardization, and training while leveraging AI tools to improve design efficiency and PPA.

Design and validate advanced analog mixed-signal circuits for HBM products including amplifiers, comparators, bandgap refs, LDOs, charge pumps, oscillators, DLLs and IOs (DDR/LPDDR). Drive layout, EM/IR optimization, parasitic modeling, tape-out revisions, reliability verification, and cross-functional integration with power delivery, process, test, and product teams. Use industry simulators and AI tools to improve PPA and delivery.

Lead physical design implementation and integration at block/subsystem/sub-chip/SoC levels including floorplanning, synthesis, placement, CTS, routing, STA, physical verification, formal equivalency, power integrity (IR-drop/EM) and tapeout readiness. Drive PD flow automation, team delivery against milestones, vendor/IP evaluations, and report progress, issues, and risks to management.

Design and architect high-performance blocks for networking ASICs. Perform micro-architecture and Verilog RTL logic design to maximize throughput and minimize power. Collaborate with verification and physical design teams on testplans, debug failures, timing constraints, and timing fixes for high-speed interfaces and memory subsystems.

Lead the design and development of analog and mixed-signal circuits for high-speed IO and connectivity products. Responsibilities include transistor-level design, simulation, verification, optimization, layout collaboration, silicon bring-up, characterization, debugging, and design closure across performance, reliability, and yield metrics. The role also involves cross-functional technical leadership, design reviews, methodology development, and mentoring junior engineers.

Lead die- and block-level physical implementation for advanced-node SoCs: floorplanning, full-chip place-and-route, PDN design, CTS, timing-driven closure, physical verification to GDSII, and develop/maintain PnR automation (Tcl/Python). Collaborate with RTL, synthesis, DFT, STA and package teams and support synthesis/STA sign-off using Fusion Compiler and PrimeTime.

Lead synthesis, logical equivalence checking, low-power verification, and physical synthesis closure for complex ASIC/SoC design blocks. Own LEC and CLP sign-off, debug equivalence failures, develop constraints, drive PPA closure, resolve power-domain issues, improve design methodologies, and maintain technical documentation. Collaborate across RTL, synthesis, physical design, and DFT teams while supporting multi-corner, multi-mode sign-off.

Lead hands-on synthesis, LEC, CLP, and power-intent flows for advanced ASIC and SoC designs. Debug Genus synthesis, Conformal LEC, constraint, and power-intent issues; write ECO scripts and timing or power constraints; support CLP sign-off; triage issues; and collaborate with physical design, DFT, and RTL teams to achieve design closure.

Supports ASIC design-flow execution, including logical equivalence checking, logic synthesis, low-power jobs, constraint reviews, status tracking, ECO scripting, and documentation. The role develops expertise in synthesis, LEC, and low-power design while using Tcl, Perl, Python, or Unix shell scripting. Candidates need an electronics or electrical engineering degree, basic ASIC-flow knowledge, scripting ability, and strong analytical and communication skills.

Leads digital architecture and RTL development for power management ICs, including LED, SiC, smartFET, and eFuse products. Responsibilities include low-power design, synthesis, timing analysis, physical-design collaboration, pre-silicon bring-up, post-silicon validation, failure analysis, and customer or production issue resolution. The role coordinates with global analog, digital, verification, firmware, systems, and project teams while owning technical outcomes for complex ASIC and mixed-signal SoC designs.

Leads innovation and development of analog IP designs, including voltage regulators, LDOs, references, charge pumps, sensors, oscillators, and ADCs. Collaborates with global analog teams, integrates IP into complex systems, develops robust design methodologies, characterizes silicon, and provides technical leadership and mentorship to junior engineers.

Performs semiconductor physical design and integration at block, subsystem, sub-chip, and full-chip levels. Responsibilities include floorplanning, synthesis, placement, clock-tree synthesis, routing, static timing, physical verification, formal equivalency, power optimization, IR-drop, and electromigration analysis. The engineer may develop and automate physical design flows, evaluate technology and IP options, support vendor selection, communicate program risks, and contribute to complex ASIC tapeouts.

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

Create and edit 3D CATIA surface and solid models; produce main and sub-assembly and installation drawings; perform virtual build-ups, 1D tolerance stack-ups, and ballooned drawings; generate BOMs from CATIA and track requirements; participate in DFMEA/PFMEA, risk and concern management; pre-fill design review documents and check preferred parts/processes.

Design and integrate complex analog and custom digital blocks for advanced DRAM (HBM) products, perform parasitic modeling, validation, and tape-out revisions; oversee layout (floor-planning, placement, routing), run simulations with industry simulators, collaborate across functions for manufacturability, mentor junior designers, and apply AI/agentic AI tools (e.g., Claude) to optimize PPA and delivery.

Lead circuit design analysis and methodology development for CPU memory blocks and datapath subsystems targeting high-frequency, low-power designs. Responsibilities include SRAM/RF/ROM design, static timing analysis, layout and floorplanning collaboration, back-end implementation, post-silicon memory analysis, and statistical variation analysis. The role also involves scripting, synthesis, place-and-route tools, Verilog, and SPICE simulations.

Leads analog IC design teams developing power management products from product definition through manufacturing release. Responsibilities include architecture and circuit design, IP development, verification, silicon evaluation, layout oversight, test planning, customer engagement, production transfer, project scheduling, and technical mentorship. The role also owns complex SoC-level outcomes and supports hiring, personnel development, and collaboration with global engineering teams.

Design and deliver analog power-management IP blocks from specification through verification and silicon validation. Responsibilities include circuit design, simulation, reliability and PVT analysis, layout guidance, technical reviews, debugging silicon issues, and collaboration with validation, product, test, and layout engineering teams. The role covers regulators, gate drivers, control loops, and complex mixed-signal designs while ensuring alignment with full-chip schedules.

Responsible for detailed electrical engineering of ground- and roof-mounted solar projects, including system sizing, layouts, single-line diagrams, SCADA architecture, performance estimation, bills of material, as-built drawings, and plant handover documentation. Coordinates with customers, project teams, supply chain, quality, and operations to ensure accurate and timely engineering deliverables. Requires solar design expertise and proficiency with PVSYST, Helioscope, AutoCAD, Google SketchUp, and MS Office.