Top Design Engineer Jobs in Bangalore

Design and deliver signoff-quality silicon layouts for leading-edge AI chips using state-of-the-art EDA tools and in-house flows. Responsibilities include floorplanning, synthesis, place-and-route, timing closure, physical verification, flow/tool enhancement, debugging complex issues, and cross-team collaboration with architecture, packaging, and foundry partners.

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

Deliver microarchitecture and RTL for Graphcore silicon: integrate IP/subsystems into SoC, maintain build/config environments, run synthesis/lint/CDC/timing checks, support verification and physical design handoffs, debug integration issues, improve automation and integration flows, and produce high-quality documentation.

Design and develop high-speed memory PHYs, overseeing sub-systems and mentoring teams while ensuring quality and schedule adherence.

Design, implement, and integrate complex analog circuits and custom digital blocks for advanced DRAM products. Perform parasitic modeling, simulation, layout oversight (floor-planning, placement, routing), tape-out activities, cross-functional coordination, and mentor junior designers. Leverage AI tools and agentic models (e.g., Claude) to improve engineering efficiency and PPA.

Lead ASIC physical design for enterprise SSD processors/controllers including floorplanning, placement, CTS, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC, tape-out. Drive APR flow development, PPA analysis, advanced-node (5nm/3nm) implementation, Redhawk-SC/Innovus/Tempus/Calibre tool usage, and manage subsystem team deliverables.

Design and integrate complex analog circuits (amplifiers, comparators, bandgaps, LDOs, charge pumps, oscillators, DLLs, IOs, sensors), develop custom digital blocks, perform parasitic modeling and simulation, manage layout and tape-out, collaborate cross-functionally for manufacturability, mentor junior designers, and apply agentic AI tools to improve PPA and delivery.

Lead analog design efforts for high-speed PHY sub-blocks at advanced process nodes (12nm and below). Own specifications and implementation, collaborate with a skilled analog team, and leverage AI-assisted design workflows where applicable.

Design and implement timing-critical RTL blocks (FSMs, power/reset logic, register banks, telemetry), ensure nanometer-process-aware, CDC- and power-aware RTL, integrate and debug into top-level designs, support verification and timing closure, participate in design reviews, and document block functionality.

Design and integrate complex analog circuits and custom digital blocks for advanced DRAM products. Lead parasitic modeling, verification and tape-out activities, manage layout (floor-planning, placement, routing), collaborate across functions for manufacturability, and mentor junior designers. Leverage agentic AI tools like Claude to improve PPA and delivery.

As a Senior Engineer in ASIC Design, you'll develop and document ASIC IP blocks, optimize design methodologies, and collaborate on cutting-edge 5G and 6G technologies.

Create and edit 3D CATIA surface and solid models; produce main and sub-assembly and installation drawings; perform virtual build-ups, 1D tolerance stack-ups, and ballooned drawings; generate BOMs from CATIA and track requirements; participate in DFMEA/PFMEA, risk and concern management; pre-fill design review documents and check preferred parts/processes.

Design and implement complex analog circuits for advanced DRAM products, oversee layout processes, validate designs, and mentor junior engineers. Collaborate across multiple teams to enhance product manufacturability using AI tools.

Design and integrate complex analog and custom digital circuits for advanced DRAM products; perform parasitic modeling, validation, tape-out revisions, and verification using industry simulators; oversee layout, floor-planning, placement, and routing; collaborate across engineering and product teams; mentor junior designers; apply AI tools (e.g., Claude, agentic AI) to improve PPA and delivery.

The role involves ownership and design of analog sub-blocks in high-speed PHYs, mentoring junior engineers, and collaborating on complex circuit designs.

Design and integrate complex analog circuits and custom digital blocks for advanced DRAM (HBM) products. Perform parasitic modeling, verification/simulation, layout oversight (floor-planning, placement, routing), tape-out support, and cross-functional collaboration. Mentor junior designers and apply AI/agent tools (e.g., Claude) to improve PPA and delivery.

Design, implement, and integrate complex analog circuits for advanced DRAM products, managing layouts, verification, and mentoring junior designers while collaborating across groups.

Design and validate complex analog mixed-signal circuits for advanced HBM products including amplifiers, comparators, references, IO (DDR/LPDDR), charge pumps, oscillators, DLLs, and sensors. Lead layout, floor-planning, placement, routing and EM/IR optimization. Perform simulations with FINESIM/HSPICE/Verilog, parasitic modeling, reliability/degradation verification, tape-out support, and cross-functional collaboration. Provide technical leadership, standardization, and training while leveraging AI tools to improve design efficiency and PPA.

Design and optimize analog and mixed-signal circuits and layouts for advanced DRAM products, including power-management IPs (bandgaps, references, regulators, charge pumps, amplifiers, comparators). Perform parasitic modeling, simulation/verification, layout (floor-planning, placement, routing), tape-out support, and cross-functional collaboration to ensure manufacturability and drive innovation across memory generations.

Lead design, implementation, and integration of complex analog circuits and custom digital blocks for advanced DRAM products. Perform parasitic modeling, verification with industry simulators, oversee layout/floorplanning and tape-out revisions, collaborate across manufacturing and product teams, mentor junior designers, and apply agentic AI (e.g., Claude) to improve PPA and delivery.

Design and integrate complex analog and custom digital blocks for advanced DRAM (HBM) products, perform parasitic modeling, validation, and tape-out revisions; oversee layout (floor-planning, placement, routing), run simulations with industry simulators, collaborate across functions for manufacturability, mentor junior designers, and apply AI/agentic AI tools (e.g., Claude) to optimize PPA and delivery.

Provide pre-sales technical support for fire alarm and detection systems: translate customer needs, advise on products and system options, prepare technical input for proposals, and collaborate with sales to ensure compliant, customer-focused fire protection solutions.

Lead end-to-end PCIe system design for NVMe SSDs across client and server platforms. Own Gen5/Gen6 PCIe architecture, PHY/MAC IP review, SoC/ASIC integration, SFR/register and firmware guidelines, link bring-up/debug, power state coordination, and platform interoperability. Act as cross-team technical authority and drive performance, reliability, and power/latency tuning.

Design and verify advanced analog and mixed-signal circuits (PLLs, LC oscillators, clocking) in advanced process nodes. Extract chip parameters, create test plans, optimize for power/performance/area/timing/yield, collaborate with architecture and layout teams, and use transistor-level simulation and solver tools for inductor characterization and post-layout verification.

Design and implement microarchitecture and RTL for mixed-signal, high-speed IPs using SystemVerilog. Optimize power, performance, and area; run lint/CDC/synthesis QA; perform power and performance analysis; review verification plans and resolve RTL issues; support SoC integration and deliver IP modules; develop automation for coverage closure and timing convergence.