Top Design Engineer Jobs in Bangalore

The Staff ASIC Physical Design Engineer will handle physical design implementation, including floorplanning, placement, routing, and timing closure for ASICs, focusing on low power designs and advanced technologies.

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

As a Silicon Logical Design Engineer, you will produce high-quality microarchitecture and RTL, collaborate across teams, and help ensure successful chip delivery.

Design and manage electronic hardware for automotive powertrain systems, review development documents, coordinate suppliers, support change control boards, explain decisions to customers, and produce reports/presentations using MS Office.

The Staff ASIC Physical Design Engineer will develop block-level physical design for ASICs, focusing on low power implementation, timing closure, and physical verification. Required skills include expertise with Cadence tools and advanced process technologies, alongside strong analytical and interpersonal abilities.

Seeking skilled silicon physical design engineers to develop AI superchips, utilizing advanced technologies, enhancing design flows, and problem-solving collaboratively.

As a Senior Engineer in ASIC Design, you'll develop and document ASIC IP blocks, optimize design methodologies, and collaborate on cutting-edge 5G and 6G technologies.

As a Memory Mask Design Engineer at NVIDIA, you'll implement high-performance CMOS integrated circuit layouts, specifically for digital memory, while using advanced EDA tools and following industry standards.

As a Logic Design Engineer at Intel, you will drive innovation by applying technical skills to projects, troubleshoot issues, and collaborate with teams to optimize solutions.

Join the ASIC design team to automate CAD flows, develop RTL IP modules, and collaborate on methodologies for ASIC development, enhancing design quality and efficiency.

Design and implement complex analog circuits for advanced DRAM products, oversee layout processes, validate designs, and mentor junior engineers. Collaborate across multiple teams to enhance product manufacturability using AI tools.

The Physical Design Engineer will perform synthesis, timing closure, and integration tasks, collaborating with the RTL team to optimize design flow.

The role involves translating system requirements into hardware specifications, digital design, RTL coding, and collaborating with verification and physical design teams.

As a Senior Circuit Design Engineer, you will craft and validate circuit IPs, improve chip performance, and mentor junior engineers.

This role involves supporting analog and mixed signal IP development by executing custom layout implementation and physical verification tasks for SoC and IP designs under supervision.

The Mixed Signal Logic Design Engineer will develop logic design and RTL coding for mixed signal subsystems, collaborate on interfaces, optimize designs, conduct static timing analysis, and provide design documentation.

As a Staff Digital IC Design Engineer, you will architect and implement MCU and DSP systems, consult on integration, lead project activities, and contribute to design improvements.

Design and develop analog and mixed-signal circuits for embedded Flash Memory, collaborating with teams to optimize performance and reliability while mitigating risks.

Design and optimize structural and thermal components for the e^pump, ensuring manufacturability while meeting safety requirements. Collaborate with teams on refining designs based on feedback and validate product performance through comprehensive testing and analysis.

The role involves designing GPU floorplans, optimizing chip areas, solving timing/congestion issues, and collaborating with various teams to improve designs.

Join NVIDIA's 'Layout Methodology' team to enhance layout creation and market speed for SRAM and custom Analog layouts, utilizing advanced technologies.

Design and implement micro-architectures in RTL for memory subsystems, verify functionality, and collaborate with cross-functional teams for debugging and synthesis.

The IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in FPGA's, develop analog circuits for IO applications, work with design requirements, optimize circuits, and support post-tapeout phase.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.

The role involves developing and testing customized DSP instructions for AI and video processing applications, optimizing algorithms, and collaborating with hardware teams.