Top Design Engineer Jobs in Bangalore

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

The Staff ASIC Physical Design Engineer will develop block-level physical design for ASICs, focusing on low power implementation, timing closure, and physical verification. Required skills include expertise with Cadence tools and advanced process technologies, alongside strong analytical and interpersonal abilities.

Seeking skilled silicon physical design engineers to develop AI superchips, utilizing advanced technologies, enhancing design flows, and problem-solving collaboratively.

The DFT Design Engineer will design custom digital DFT circuits, define testability features, and perform simulations, collaborating with other designers and product engineering.

Design and develop custom digital DFT circuits, implement testability features, collaborate with engineers, and perform circuit simulations to enhance memory testability.

The Staff Engineer will focus on RTL design, SoC integration, and collaborate with cross-functional teams while leveraging AI skills.

The role involves designing and optimizing analog circuits, managing layout processes, and collaborating with various teams for product manufacturability. It includes mentoring junior engineers and contributing to innovation in memory technology.

The lead electro-mechanical engineer will design and develop components, manage requirements, lead issue resolution in production, and collaborate across technical teams.

As a Silicon Logical Design Engineer, you will produce high-quality microarchitecture and RTL, collaborate across teams, and help ensure successful chip delivery.

Design and implement complex analog circuits for advanced DRAM products, oversee layout processes, validate designs, and mentor junior engineers. Collaborate across multiple teams to enhance product manufacturability using AI tools.

Lead physical design and implementation of semiconductor circuits, mentor engineers, ensure timely product delivery, and optimize design methodologies.

Design and implement micro-architectures in RTL for memory subsystems, verify functionality, and collaborate with cross-functional teams for debugging and synthesis.

Lead full RTL-to-GDSII physical design for complex SoCs, develop and optimize advanced PD methodologies, ensure timing/power/area targets, perform verification and power integrity analyses, mentor engineers, and drive tool/process improvements for successful tape-outs.

The Principal IC Package Design Engineer leads flip-chip package design focusing on signal integrity, power integrity, and thermal optimization while collaborating with cross-functional teams and customers to deliver high-performance solutions.

The role involves leading mechanical design activities for aeroderivative gas turbines, including 3D modeling, FEM analysis, and cross-functional coordination.

Lead the design and development of aeroderivative gas turbine systems and components, managing mechanical design activities, durability analysis, and cross-functional collaboration.

Lead physical design activities for GPUs and ASICs, focusing on design implementation, troubleshooting, and process improvements. Collaborate with teams to address design challenges and improve RTL2GDS flow.

Develop and design software systems for Hybrid Cloud and deploy them in production environments, collaborating with product management.

Define and design high-performance ASIC blocks, collaborate with verification and physical design teams, and debug ASIC issues.

The ASIC Design Engineer will define and architect ASIC blocks, perform micro-architecture and logic design, and collaborate on testing and physical design for high-performance networking ASICs.

The engineer is responsible for physical implementation from RTL to GDS, including design optimization, verification, and collaboration with teams. Requires 8+ years of experience.

Design and optimize sheet metal components and thermal systems for the e^pump with a focus on manufacturability and performance requirements.

Drive Intel's CPU design in DFT, focusing on RTL implementation, verification, and other DFT features. Requires deep experience in test design and help with post-silicon support.

The Sr. Mask Design Engineer will layout and verify analog and mixed signal circuits, using Cadence tools and collaborating with designers for optimal circuit performance.

The Senior R&D Hardware Design Engineer will lead complex hardware designs, focusing on high-speed digital systems, mentoring junior engineers and collaborating across teams for production-ready designs.