Job Summary
We are seeking a highly skilled RTL Design Engineer with deep expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team. The candidate will be responsible for designing, implementing, and verifying RTL for PCIe controllers and related subsystems, ensuring compliance with protocol standards and performance targets.
Key Responsibilities
- Architect and implement RTL for PCIe IP blocks
- Collaborate with system architects to define micro-architecture and design specifications.
- Responsible for the quality of Design Quality. Expertise in LINT/CDC, Synthesis is Must.
- Work closely with verification teams to develop testbenches and validate functionality.
- Participate in interoperability testing
- Contribute to performance, power, and area optimization in advanced nodes.
- Interface with cross-functional teams including PHY, software, and validation.
Required Skills
- Strong hands-on experience in RTL design using Verilog/SystemVerilog.
- Deep understanding of PCIe protocol stack and transaction layers.
- Experience with AXI & PXC interfaces, DMA engines, and MSI interrupt handling,
- Familiarity with CDC design principles and asynchronous FIFO implementation.
- Proficiency in synthesis, linting, and static timing analysis.
- Exposure to formal verification and assertion-based design methodologies.
- Experience with simulation tools and waveform debugging.
Education
- Bachelor’s or Master’s degree in Electronics /Electrical Engineering , or related field.
Skills Required
- BE/BTech/ME/MTech in Electrical/Electronics/VLSI
- 8-14 years of experience
- Experience in RTL design using Verilog
- Experience with System Verilog
- Experience with UVM based environment
- Experience with PCIe
- CXL/PXC experience
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
