Top Design Engineer Jobs in Bangalore

Lead verification for complex CPU/SoC IP and subsystems: define verification strategies and test plans, build verification environments, run and debug simulations/emulations, apply random-stimulus and coverage-driven techniques, and mentor engineers while improving verification methodologies and tools.

Lead the design and development of SSD hardware, ensuring compliance with standards, collaborating with cross-functional teams, and automating validation tests.

Design, implement and integrate complex analog circuits and custom digital blocks for advanced DRAM (HBM) products. Perform parasitic modeling, verification with industry simulators, manage layout/floorplanning, collaborate with cross-functional teams for manufacturability, mentor junior designers, and use agentic AI tools (e.g., Claude) to optimize PPA and accelerate delivery.

Design and verify complex digital and mixed-signal IP for automotive, industrial, and medical products. Define architectures, conduct feasibility studies, lead sub-project teams, support SoC integration, collaborate on DFT and production testing, and document designs and safety mechanisms. The role requires ultra-low-power digital design using Verilog/SystemVerilog, technical leadership, and strong communication skills.

Design and verify complex CPU/SoC IP by planning verification, building constrained-random UVM or C/C++ test environments, or using formal SVA tools. Debug RTL (Verilog) in simulation/emulation, write functional coverage, and close verification holes to meet tape-out requirements.

Assess and assure software quality for cloud-native SaaS products by conducting design and release readiness reviews, instrumenting CI/CD and observability, defining test strategies, triaging flaky tests, and collaborating cross-functionally to mitigate risks and ensure release criteria are met.

Design and verify digital integrated circuits for TI products, including processor, memory-management, multicore, and cache architectures. Responsibilities include defining specifications, analyzing architecture trade-offs, participating in design reviews, supervising IC layouts, developing behavioral models, characterizing prototypes, creating test specifications, and coordinating with test and product engineering teams to support product releases.

Own end-to-end design verification for IOMMU and system IP, including specification review, test planning, constrained-random verification, coverage analysis, regression debugging, and sign-off. Build scalable SystemVerilog/UVM environments, verify standard bus protocols, automate workflows with scripting, and collaborate with architecture, RTL, and validation teams. The role is hybrid in Bangalore and involves CPU and memory-management IP for AI/ML systems.

Design and verify SoC Design-for-Test architectures, including ATPG, MBIST, LBIST, scan insertion, and analog test features. Generate and optimize test patterns, integrate DFT into RTL and physical design, develop automation scripts, analyze silicon and production test data, debug root causes, and document implementations. Collaborate with design, verification, backend, and test engineering teams throughout the silicon lifecycle.

Designs and validates analog and mixed-signal integrated circuits from architecture and schematic through post-layout simulation and silicon validation. Uses MATLAB and Cadence for circuit design, simulation, modeling, and data analysis. Performs feedback, stability, reliability, debugging, and root-cause analysis. Collaborates with systems, layout, test, verification, and digital design teams throughout product development, contributing to design reviews, characterization, documentation, and technical presentations.

Designs and analyzes bridge structures using structural engineering software and applicable design codes. Produces technical drawings, calculations, specifications, reports, and construction documentation; collaborates with multidisciplinary teams; evaluates geotechnical and environmental factors; supports site inspections, proposals, cost estimates, and project coordination; and mentors junior engineers.

The job description provides limited role-specific information. The Design Engineer (Geotech) position is associated with geotechnical design and engineering services supporting sustainable infrastructure and development projects.

The posting provides company and culture information but does not specify the Design Engineer’s responsibilities, qualifications, technologies, location, travel, or project details. The role title indicates a drainage-focused engineering position within Egis’s architecture, consulting, and construction engineering organization.

Lead an analog IC design team through product definition, design, verification, silicon evaluation, validation, and manufacturing release. Guide physical design and layout, coordinate with systems, applications, marketing, product, validation, and test engineering teams, support customer discussions, contribute to product roadmaps, and help hire, develop, and evaluate personnel.

Designs high-speed mixed-signal communication chips and digital circuits interfacing with analog circuitry. Responsibilities include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging, test method development, specifications, application materials, datasheets, and demo boards. Collaborates closely with analog and digital engineering teams to solve complex problems and deliver projects on time.

Designs high-speed mixed-signal communication chips and digital circuits interfacing with analog circuitry. Responsibilities include RTL coding, simulation, synthesis, timing closure, verification, evaluation, and debugging at circuit and behavioral levels. The role also develops test methods, specifications, application materials, data sheets, and demo boards while collaborating closely with analog and digital engineering teams.

Designs and develops high-speed hardware boards for service provider routers, including schematic capture, SERDES and signal-integrity implementation, hardware bring-up, product qualification, lab debugging, and sustaining support. Collaborates with ASIC, FPGA, software, vendors, and cross-functional teams across the hardware lifecycle. Responsibilities include troubleshooting field issues, failure analysis, design validation, and supporting products through release and production.

Own full RTL-to-GDSII physical design implementation for complex mixed-signal and digital semiconductor designs. Responsibilities include synthesis, floorplanning, place-and-route, clock tree synthesis, timing and power closure, ECOs, sign-off analysis, physical verification, UPF-driven low-power design, scripting automation, EDA tool evaluation, and AI methodology integration.

Design and implement DFT circuitry including scan architecture, JTAG, Memory BIST, and memory repair. Perform DFT verification through gate-level simulations, debug simulation failures and DRC issues, improve ATPG coverage, analyze DFT timing constraints, and support post-silicon and manufacturing teams with ATE debugging.

Design and verify high-speed, low-power analog mixed-signal SerDes transceivers for data-center, networking, AI, and HPC applications. Translate system requirements into circuit architectures, optimize performance across process and environmental conditions, develop behavioral models, collaborate on layout and signal integrity, and support tapeout, silicon bring-up, characterization, debugging, and production release.

Design and manage electrical systems for mineral processing equipment, including schematics, bills of materials, control panels, cable routing, and 3D electrical-mechanical integration. Coordinate multiple projects, support installation and commissioning, apply international electrical standards, and collaborate with cross-functional teams. The role also contributes to design standardization, continuous improvement, and field support at sites and workshops.

Design and verify memory layouts for advanced CMOS processes, including floor planning, hierarchical layout, chip integration, and physical verification. Manage schedules and end-to-end deliverables while applying process rules and layout guidelines. Collaborate with SOC and library teams, support new methodology reviews, and lead or train junior engineers. Experience with memory architecture, memory compilers, signal and power planning, and automation is valuable.

Develop and execute comprehensive digital design verification strategies for analog and mixed-signal ICs. Build UVM testbenches, run RTL and gate-level simulations, manage regressions and coverage closure, and debug complex design issues. Apply formal verification, CDC/RDC assertions, low-power verification with UPF, and protocol checks. Support post-silicon characterization and ATE pattern generation while collaborating with architecture, design, firmware, product, and application engineering teams.

Owns analog and mixed-signal IP and full-chip design verification from specification through post-silicon closure. Responsibilities include defining verification strategies and plans, developing UVM testbenches, creating behavioral models and coverage monitors, executing RTL and gate-level simulations, applying formal verification, debugging designs, and collaborating with architecture, RTL, physical design, DFT, systems, firmware, analog, and applications teams.

Leads architecture and design verification for digital blocks in ASIC-based SoC designs. Develops power, performance, and area-optimized microarchitectures; manages Lint, CDC, formal equivalence, ECO, and scripting flows; collaborates with geographically distributed teams; mentors engineers; and supports post-silicon debugging. Designs must be realized in silicon through ASIC tapeouts rather than FPGA implementations.