Top Design Engineer Jobs in Bangalore

Design and develop reusable IP blocks for SoC integration: create micro-architecture, implement RTL (Verilog/SystemVerilog/VHDL), optimize for PPA, run lint/CDC/synthesis/STA checks, drive bug fixes, support sign-off, and collaborate with verification and cross-functional teams through silicon bring-up.

Develop and implement firmware for high-speed SERDES IP across architecture, implementation, verification, testing, and customer deployment. Build prototype control software, support FuSa-compliant firmware, assist post-silicon validation and debugging, provide hot fixes during customer deployments, and maintain design and compliance documentation.

The staff engineer will work on ASIC physical design including floorplanning, routing, timing closure, and physical verification, with a focus on enterprise SSD design.

Design and optimize SoC IO/pad rings and bump patterns, define IO connectivity, produce physical deliverables (DEF, netlists), integrate JTAG TAP controllers, collaborate with cross-functional teams, and support verification, emulation, and post-silicon lab validation including debug and logic workarounds.

The Mechanical Design Engineer will perform engineering analysis, design layouts, and coordinate procurement for mechanical components, while ensuring adherence to standards throughout the product lifecycle.

Lead an Analog IC design team, guide design processes, collaborate with cross-functional teams, and ensure product development from definition to manufacturing.

Lead complex digital design projects, define architectures, mentor engineers, and collaborate across functions to drive innovation in digital design.

The Staff Physical Design Engineer oversees end-to-end physical design for complex SoCs, leads a team, and drives methodology improvements while mentoring junior engineers and communicating across departments.

Lead the development of Physical Design Methodologies for digital flows using EDA tools, automate CAD solutions, and ensure successful tapeouts.

Lead end-to-end hardware design for high-speed, high-density Ethernet switches: specify components, capture schematics, collaborate on PCB layout and signal/power integrity simulations, drive lab bring-up and production ramp, work with CMs, and mentor junior engineers.

Lead analog/mixed-signal IC design for high-speed D2D and SERDES products from concept through verification. Collaborate with layout engineers and global teams on circuit blocks (drivers, receivers, PLLs, phase interpolators, bias/bandgap, regulators) using CAD simulation, layout, and physical verification tools. Support architecture and silicon evaluation.

Lead analog/mixed-signal design for high-speed Die-to-Die (D2D) and SERDES products at advanced process nodes. Develop circuit blocks from concept through verification, collaborate with layout engineers and technical leads, and work with global teams using CAD simulation, layout, and physical verification tools. Support silicon evaluation and lab testing.

Lead analog/mixed-signal IC design for high-speed Die-to-Die and SERDES products from concept through verification. Collaborate with layout engineers and technical leads, work across global teams, and ensure conformance to customer specs using CAD simulation, layout, and physical verification tools.

Lead analog/mixed-signal IC design for high-speed D2D and SERDES products at advanced nodes. Develop circuit blocks from spec through verification, collaborate with layout and architecture leads, and work with global teams. Use CAD tools for simulation, layout and physical verification; support silicon evaluation and lab testing.

Design and execute advanced semiconductor package layouts (2.5D/3D, FCBGA, SiP, chiplets), maintain CAD databases, generate manufacturing outputs, ensure DFM/DFA compliance, collaborate with SI/PI, thermal and reliability teams, and manage ECO/version control throughout the design lifecycle.

Lead design and ownership of complex analog IPs and small ICs (PMICs, LDOs, DC-DC converters). Define block specs, implement and compensate control loops, work through layout and parasitic extraction, run simulations and silicon bring-up, mentor engineers, establish design flows, and ensure production-quality silicon with IO protection and ESD/latch-up mitigation.

Lead a team of design engineers in delivering high-impact ASIC IP solutions, overseeing project alignment, and fostering innovation and cross-team collaboration.

Design, model, and produce conveyor, ASRS, and material handling equipment using SolidWorks and AutoCAD; perform mechanical calculations, tolerance analysis, component selection, FEA, and DFMEA; collaborate with cross-functional teams, support prototyping, produce manufacturing drawings, BOMs, technical documentation, and ensure compliance with standards.

The Lead Design Engineer develops firmware for DDR5 PHY, collaborates with hardware designers, and verifies firmware on simulations and silicon boards.

The Principal Design Engineer will oversee integration and verification of DDR IP subsystems, support silicon bring-up, and resolve complex integration issues while working with global teams.

The Design Engineer will create and verify technical drawings, support manufacturing processes, coordinate project activities, and ensure customer requirements are met.

The Principal Design Engineer will design high-speed analog and mixed-signal circuits, lead design reviews, and collaborate across teams on HBM PHY products.

Develop firmware for DDR/LPDDR/GDDR/HBM PHY, collaborate on algorithms, and support debugging of firmware simulations and hardware.

The candidate will lead HBM PHY SI/PI design, make technical decisions, coordinate deliverables, and conduct project gate design reviews.

Responsible for IC verification and validation, developing test architectures, managing schedules, and supporting technical communication with suppliers for ASIC projects.