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The Role
Design and implement DFT circuitry including scan architecture, JTAG, Memory BIST, and memory repair. Perform DFT verification through gate-level simulations, debug simulation failures and DRC issues, improve ATPG coverage, analyze DFT timing constraints, and support post-silicon and manufacturing teams with ATE debugging.
Summary Generated by Built In
Job Details:Job Description:
- Strong knowledge and experience in Spyglass DFT, Scan Architecture (SSN Topology), ATPG and various fault models.
- Hands on skills to implement JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry using industry standard tools.
- Hands on experience in DFT verification using Gate Level Simulations with timing annotations.
- Hands on experience in solving DFT problems, simulation failures, ATPG coverage improvements and DRC debug.
- Good understanding of timing constraints and DFT mode timing analysis.
- Proficiency in RTL coding, shell scripting.
- Experience working with post-Silicon/manufacturing teams on ATE, including debugging and resolving issues.
Job Type:Intel Contract EmployeeShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- B.E., B.Tech., M.E., or M.Tech. degree in Electrical, Electronics, Communication, or a related engineering discipline
- 2+ years of Design For Test experience
- Strong knowledge and experience with Spyglass DFT, scan architecture, SSN topology, ATPG, and fault models
- Hands-on experience implementing JTAG, Memory BIST, and Memory Repair circuitry using industry-standard tools
- Hands-on experience with DFT verification using gate-level simulations with timing annotations
- Experience debugging DFT problems, simulation failures, ATPG coverage, and DRC issues
- Understanding of timing constraints and DFT mode timing analysis
- Proficiency in RTL coding and shell scripting
- Experience working with post-silicon or manufacturing teams on ATE debugging and issue resolution
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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