Top Design Engineer Jobs in Bangalore

The Principal Design Engineer will develop and implement custom accelerator SoCs, focusing on design verification using System Verilog and UVM. Responsibilities include test plan execution, test-bench maintenance, and collaboration across teams to ensure effective verification of complex systems.

Lead Design for Test activities for SoCs, define and implement DFT architecture, perform simulations, and collaborate with teams for ASIC development.

The Lead Design Engineer will oversee design verification projects, focusing on complex designs with a strong emphasis on functional verification fundamentals and hands-on coding with System Verilog and UVM.

Manage the design of ASIC with advanced techniques in RTL coding and complex path designs, ensuring compliance with key protocols and performing simulations.

As a Principal Design Engineer, you'll work with IC design teams on quality management, improvements, and analysis, ensuring high standards in semiconductor products.

The role involves enhancing existing verification environments, developing new methodologies, and collaborating with various design teams. Requires strong functional verification skills and prior digital verification experience.

The Principal Design Engineer will support DDR IP subsystems integration, resolve complex issues, perform simulations, assist customers, and enhance their experience.

The role involves design verification for IP development, including UVM testbench creation, formal verification, and design strategy formulation.

The Principal Design Engineer will focus on design verification for IP development, utilizing UVM for testbench creation and formal verification while coordinating with teams to ensure high-quality outputs.

As a Lead Design Engineer at Cadence, you will develop firmware for memory interfaces, collaborate with hardware designers, and support debugging of simulations and boards.

The role involves physical layer electrical validation of high-speed SERDES protocols, utilizing lab equipment, and possibly leading small teams in post-silicon validation efforts.

Design and support RTL for DDR Memory Controller, ensuring compliance with guidelines, verifying features, and assisting customers in configurations.

Develop firmware for DDR PHY using microcontrollers, collaborate with hardware designers, implement algorithms, and support firmware verification.

As a Principal Design Engineer at Cadence, you will perform design verification of ASICs, create test plans, and engage in post-silicon validation.

The role involves designing embedded systems, optimizing algorithms, programming in C/C++, and collaborating with cross-functional teams for innovative electronic products.

The Principal DFT Design Engineer will mentor junior staff, drive innovation in design for test methodologies, and collaborate on project deliverables while utilizing EDA tools and ensuring coverage analysis.

The Lead Design Engineer will integrate and verify IP solutions, working on RTL integration, compliance with design guidelines, and customer support.