Top Design Engineer Jobs in Bangalore

Lead analog/mixed-signal IC design for high-speed D2D and SERDES products from concept through verification. Collaborate with layout engineers and global teams on circuit blocks (drivers, receivers, PLLs, phase interpolators, bias/bandgap, regulators) using CAD simulation, layout, and physical verification tools. Support architecture and silicon evaluation.

The Principal Design Engineer will design high-speed analog and mixed-signal circuits, lead design reviews, and collaborate across teams on HBM PHY products.

Lead analog/mixed-signal IC design for high-speed D2D and SERDES products at advanced nodes. Develop circuit blocks from spec through verification, collaborate with layout and architecture leads, and work with global teams. Use CAD tools for simulation, layout and physical verification; support silicon evaluation and lab testing.

Develop firmware for DDR/LPDDR/GDDR/HBM PHY, collaborate on algorithms, and support debugging of firmware simulations and hardware.

Lead analog/mixed-signal IC design for high-speed Die-to-Die and SERDES products from concept through verification. Collaborate with layout engineers and technical leads, work across global teams, and ensure conformance to customer specs using CAD simulation, layout, and physical verification tools.

The Lead Design Engineer develops firmware for DDR5 PHY, collaborates with hardware designers, and verifies firmware on simulations and silicon boards.

Lead analog/mixed-signal design for high-speed Die-to-Die (D2D) and SERDES products at advanced process nodes. Develop circuit blocks from concept through verification, collaborate with layout engineers and technical leads, and work with global teams using CAD simulation, layout, and physical verification tools. Support silicon evaluation and lab testing.

The candidate will lead HBM PHY SI/PI design, make technical decisions, coordinate deliverables, and conduct project gate design reviews.

The Principal Design Engineer will oversee integration and verification of DDR IP subsystems, support silicon bring-up, and resolve complex integration issues while working with global teams.

The Design Engineer will create and verify technical drawings, support manufacturing processes, coordinate project activities, and ensure customer requirements are met.

Design and verify analog/mixed-signal ICs (PLL, DLL, ADC/DAC, CTLE, regulators, amplifiers, TX/RX, CDRs) using SPICE/Spectre/MATLAB. Architect circuits, implement designs, optimize low-power/high-speed techniques, and collaborate with system architects and global teams to deliver CMOS transceiver/SERDES products.

Architect and implement production-quality RTL for high-speed interfaces (UCIe/HBM and others). Own micro-architecture, RTL coding, synthesis, CDC/RDC and lint flows, and partner with verification and bring-up teams. Provide technical leadership, mentor junior engineers, participate in design reviews, and ensure IP quality, robustness, and reusability for silicon-proven IPs/SoCs.

Design and deliver mixed-signal DDR PHY logic: define architecture, implement RTL in SystemVerilog, ensure RTL quality using frontend tools (lint/CDC/RDC/synthesis), drive low-power and area optimizations, create FE packages and automation flows, and collaborate across validation, backend, and SoC teams.

Design and optimize analog and mixed-signal circuits for advanced process nodes. Create floorplans, perform circuit design, run pre/post-layout simulations, extract parameters, and verify functionality against specs. Develop test plans, correlate measurements to simulations, and collaborate with architecture and layout teams to meet power, performance, area, timing, and yield goals.

Design and implement digital IP and subsystems for MPU/MCU products, define microarchitecture, optimize for area, performance and low power, implement security countermeasures, integrate with SoC (CDC, RDC, Lint, DFT), and collaborate with IP architects and verification teams to debug and resolve integration issues.

The role involves designing and architecting high-performance networking ASICs, performing micro-architecture, and collaborating with verification and physical design teams.

The Senior Hardware Design Engineer will lead complex hardware designs, mentor engineers, and make key technical decisions in networking systems.

Lead hardware design for advanced networking platforms, define architecture, guide design standards, and mentor engineers in system-level solutions.

Design and architect high-performance ASIC blocks for advanced networking systems. Perform micro-architecture and RTL implementation, collaborate on verification and physical design, debug timing and functional issues, and optimize for throughput and power.

Design and architect high-performance VLSI/ASIC blocks for networking ASICs. Perform micro-architecture and Verilog RTL design, collaborate on verification and physical design, debug timing and functional issues, and optimize for throughput and power.

Design and architect high-performance ASIC blocks for advanced networking chips. Perform micro-architecture and RTL logic design for throughput and power optimization, collaborate with verification and physical design teams on testplans, timing constraints, timing fixes, and debugging.

Design and implement block-level verification environments using SystemVerilog and UVM. Develop and run verification suites with front-end simulators (VCS/Xcelium), analyze code and functional coverage, perform gate-level simulation, debug ASIC issues with designers, and build scripts to improve verification infrastructure.

Design and architect high-performance networking ASIC blocks, perform micro-architecture and RTL logic design, collaborate with verification to develop test plans and debug, and work with physical design to create timing constraints, analyze violations, and implement timing fixes.

Define and micro-architect high-performance blocks for next-generation networking ASICs. Perform RTL micro-architecture and Verilog coding, optimize throughput and power, partner with verification for test plans and debugging, and collaborate with physical design on timing constraints and closure.

Design and own RTL development for an AI-enabled RISC-V CPU core, including microarchitecture, vector/matrix engines, performance/power/area optimization, and verification support. Collaborate with cross-functional teams for timing, reliability, testability, and SoC integration.