Top Design Engineer Jobs in Bangalore

Performs physical design integration for custom GPU blocks across Gfx, Media, and SOC. Conducts layout verification and milestone reviews, provides feedback to floorplan, RDL, PDN, and clocking teams, and supports tape-in quality through timely fixes and correct-by-construction methodologies. Collaborates across teams to achieve design goals and maintain project timelines.

Leads digital architecture and RTL development for power management ICs, including LED, SiC, smartFET, and eFuse products. Responsibilities include low-power design, synthesis, timing analysis, physical-design collaboration, pre-silicon bring-up, post-silicon validation, failure analysis, and customer or production issue resolution. The role coordinates with global analog, digital, verification, firmware, systems, and project teams while owning technical outcomes for complex ASIC and mixed-signal SoC designs.

Lead ESD architecture and protection strategies, advanced circuit design, silicon-level debug, and cross-functional mentoring in high-speed I/O systems.

Owns design-stage quality for charger hardware, leading DFMEA, design verification planning, validation criteria, test reviews, failure analysis, and corrective actions. The role collaborates with hardware, firmware, and process quality teams to ensure charger architecture and components meet performance, safety, and reliability requirements. It also supports field issue analysis, fault tree documentation, design reviews, and continuous product improvement.

Verify ASIC designs, architectures, and microarchitectures for GPU memory subsystems and IP. Develop test plans, reusable verification infrastructure, bus functional models, monitors, checkers, scoreboards, and coverage-driven tests using SystemVerilog and UVM. Perform functional coverage closure, debug complex IPs, and collaborate with architects, designers, and pre- and post-silicon verification teams.

Verify NVIDIA ASIC memory subsystem and XBAR IP designs using advanced, coverage-driven methodologies. Develop test plans, tests, reusable bus functional models, monitors, checkers, scoreboards, and verification infrastructure. Apply SystemVerilog, UVM, random stimulus, functional coverage, and assertion-based verification to achieve closure. Collaborate with architects, designers, and pre- and post-silicon teams to validate complex IPs and subsystems.

Create and edit 3D CATIA surface and solid models; produce main and sub-assembly and installation drawings; perform virtual build-ups, 1D tolerance stack-ups, and ballooned drawings; generate BOMs from CATIA and track requirements; participate in DFMEA/PFMEA, risk and concern management; pre-fill design review documents and check preferred parts/processes.

Lead the architecture, transistor-level design, integration, verification, silicon validation, qualification, and production support of complex analog and mixed-signal ICs. Design power-management and analog IP, optimize performance, power, area, yield, and reliability, and collaborate on layout and chip integration. Establish simulation and design methodologies, address ESD and latch-up protection, mentor engineers, and lead a small technical team through on-schedule product delivery.

Own architecture, circuit design, verification, silicon validation, and production support for complex analog and power-management ICs. Design converters, LDOs, charge pumps, references, sensors, ADCs, and protection circuits; analyze stability, parasitics, reliability, and manufacturability. Lead tape-out and silicon debug, establish design methodologies, conduct technical reviews, mentor engineers, and influence product architecture as a senior individual contributor.

Own end-to-end physical design implementation for advanced SoCs, including floorplanning, synthesis, placement, clock tree synthesis, routing, timing closure, and physical verification. Optimize power, performance, and area using multi-voltage domains, power gating, and datapath techniques. Perform STA, signal integrity, DRC, LVS, EMIR, and equivalence checking while collaborating with RTL, DFT, and signoff teams. Automate flows with Tcl, Python, or Perl and mentor junior engineers.

Lead the architecture, transistor-level design, integration, validation, and production support of complex analog and mixed-signal ICs for power management and multi-phase controller products. Responsibilities include circuit optimization, simulation methodology, analog layout collaboration, ESD and reliability strategy, silicon debugging, technical leadership, mentoring, and managing a small engineering team.

Leads pre-silicon design verification for complex ASIC, SoC, and AI components. Responsibilities include developing UVM-based testbenches, constrained-random stimulus, scoreboards, checkers, assertions, coverage, and debugging RTL in simulation or emulation. The role collaborates with architecture and design teams, supports verification from definition through silicon, contributes to post-silicon bring-up, and provides technical leadership and mentorship.

Leads mechanical product design for water treatment equipment, including detailed design, calculations, tolerance analysis, manufacturing drawings, FEA, testing, validation, and continuous improvement. Manages project delivery, cost, quality, BOMs, value engineering, and new product development. Collaborates globally with engineering, manufacturing, suppliers, customers, and cross-functional teams while mentoring junior engineers and driving innovative, technically sound solutions.

Leads architecture, transistor-level design, simulation, verification, integration, tape-out, silicon bring-up, validation, and characterization of high-performance analog and mixed-signal IP. Designs signal-chain and power-management circuits using advanced CMOS technologies, addresses PVT variation, noise, mismatch, reliability, and low-power requirements, and collaborates across digital, system, layout, and product teams. Provides technical mentorship and drives reusable IP platforms, design methodology, innovation, and roadmap planning.

Design verification engineer responsible for pre- and post-silicon/IP/SoC verification using SV-UVM/C, developing tests and testbenches, FPGA validation, firmware bring-up, cross-functional collaboration, debugging, and improving validation methodologies and tools to ensure silicon quality and manufacturability.

Design digital low-power wireless SoCs from concept through tape-out. Responsibilities include RTL coding, synthesis, timing analysis, verification collaboration, physical design integration, silicon validation, power optimization, design reviews, and vendor/IP issue resolution. The role requires expertise in ASIC design flows, SOC architecture, bus protocols, scripting, and low-power techniques, with collaboration across international engineering teams.

Lead circuit design analysis and methodology development for CPU memory blocks and datapath subsystems targeting high-frequency, low-power designs. Responsibilities include SRAM/RF/ROM design, static timing analysis, layout and floorplanning collaboration, back-end implementation, post-silicon memory analysis, and statistical variation analysis. The role also involves scripting, synthesis, place-and-route tools, Verilog, and SPICE simulations.

Leads analog IC design teams developing power management products from product definition through manufacturing release. Responsibilities include architecture and circuit design, IP development, verification, silicon evaluation, layout oversight, test planning, customer engagement, production transfer, project scheduling, and technical mentorship. The role also owns complex SoC-level outcomes and supports hiring, personnel development, and collaboration with global engineering teams.

Design and deliver analog power-management IP blocks from specification through verification and silicon validation. Responsibilities include circuit design, simulation, reliability and PVT analysis, layout guidance, technical reviews, debugging silicon issues, and collaboration with validation, product, test, and layout engineering teams. The role covers regulators, gate drivers, control loops, and complex mixed-signal designs while ensuring alignment with full-chip schedules.

Responsible for detailed electrical engineering of ground- and roof-mounted solar projects, including system sizing, layouts, single-line diagrams, SCADA architecture, performance estimation, bills of material, as-built drawings, and plant handover documentation. Coordinates with customers, project teams, supply chain, quality, and operations to ensure accurate and timely engineering deliverables. Requires solar design expertise and proficiency with PVSYST, Helioscope, AutoCAD, Google SketchUp, and MS Office.

Designs and develops custom mechanical tooling, fixtures, layouts, drawings, and specifications for manufacturing and operational workflows. Performs engineering analyses, resolves complex mechanical challenges, establishes tooling standards, and drives continuous improvement. Leads projects from concept through implementation, defines and documents testing, reviews engineering documentation, and collaborates with suppliers, manufacturing, engineering, and leadership teams.

Designs gearbox housing, covers, brackets, deflectors, inverter boxes, fasteners, and related hybrid/e-drive components. Develops concepts and detailed designs, creates manufacturing-ready drawings, presentations, and tolerance calculations, and interprets casting simulations and CAE results. Coordinates designs with suppliers and project teams through meetings, change management, FMEA, requirements management, and interface definition. Supports prototype testing and evaluates results with test engineers.

Develops reusable analog and mixed-signal CMOS circuit blocks, including amplifiers, LDOs, bandgaps, and charge pumps. Responsibilities include circuit design, layout supervision, simulation, verification, laboratory debugging, bench characterization, post-silicon validation, DFT collaboration, documentation, and production release. Provides technical leadership in specifications, project planning, design-team coordination, and collaboration with systems, test, product, applications, and marketing teams.

Deliver microarchitecture and RTL for Graphcore silicon: integrate IP/subsystems into SoC, maintain build/config environments, run synthesis/lint/CDC/timing checks, support verification and physical design handoffs, debug integration issues, improve automation and integration flows, and produce high-quality documentation.

Designs, develops, simulates, verifies, and optimizes analog and mixed-signal circuits, including GPIO, PLLs, LDOs, and ADCs, for advanced semiconductor process nodes. Responsibilities include floor planning, parameter extraction, test planning, performance analysis, issue resolution, and power, performance, area, timing, and yield optimization. The role collaborates with architecture and layout teams to deliver robust, high-quality semiconductor IP.