Design Verification Engineer II

Reposted Yesterday
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Hiring Remotely in IN
Remote
Mid level
Software • Quantum Computing • Metaverse • Infrastructure as a Service (IaaS)
The Role
Design and verify complex CPU/SoC IP by planning verification, building constrained-random UVM or C/C++ test environments, or using formal SVA tools. Debug RTL (Verilog) in simulation/emulation, write functional coverage, and close verification holes to meet tape-out requirements.
Summary Generated by Built In
Overview

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. 

We are looking for a design verification engineer to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering (AISiE) team. The candidate should be a highly motivated self-starter who will thrive in this cutting-edge technical environment. 

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. 


Responsibilities

The AISiE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.  

  • Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios. 

  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools 

  • Develop tests using UVM or C/C++ 

  • Analyse and debug test failures with designers to deliver functionally correct design. 

  • Identify and write functional coverage for stimulus and corner cases. 

  • Close coverage to plug verification holes and meet tape out requirements. 


Qualifications
  • 3 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s 

  • knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. 

  • good understanding of computer architecture 

  • Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments 

  • Scripting language such as Python or Perl 


This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.



Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Skills Required

  • 3+ years of design verification experience delivering complex CPU or SoC IPs
  • Proficiency with SystemVerilog and UVM or formal verification using SVA and industry formal tools
  • Experience developing tests using UVM or C/C++
  • Substantial background debugging RTL (Verilog) designs and using simulation and/or emulation environments
  • Knowledge of verification principles, testbenches, stimulus generation, and functional coverage
  • Good understanding of computer architecture
  • Scripting experience with Python or Perl

Microsoft Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Microsoft and has not been reviewed or approved by Microsoft.

  • Fair & Transparent Compensation Pay is presented as broadly competitive overall, with clear role/level/location variation and an emphasis on using posted ranges and band information for apples-to-apples comparisons.
  • Retirement Support Retirement benefits are described as a standout, highlighted by a strong 401(k) match structure and immediate vesting, plus additional plan features for tax-advantaged saving.
  • Parental & Family Support Family-oriented benefits are portrayed as a meaningful strength, with substantial paid parental leave and added supports like back-up care and adoption/surrogacy assistance.

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The Company
HQ: Redmond, WA
206,870 Employees
Year Founded: 1975

What We Do

At Microsoft, our mission is to empower every person and every organization on the planet to achieve more. Our mission is grounded in both the world in which we live and the future we strive to create. Today, we live in a mobile-first, cloud-first world, and the transformation we are driving across our businesses is designed to enable Microsoft and our customers to thrive in this world.

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