Top Design Engineer Jobs in Bangalore

Architect, design, and verify complex digital front-end circuits for FPGA and ASIC, develop HDL modules and architectural specifications, drive reusable and area-optimized designs, perform design reviews, collaborate across disciplines, improve design methodologies and toolchains, and document requirements, verification strategies, and test results.

The Digital Design Engineer will develop digital logic circuits, work with analog domains, support design validation, and innovate design methodologies.

Design Engineer responsible for conveyor systems and automated material handling equipment, utilizing SolidWorks for 3D models and technical documentation.

The Associate Design Engineer will design conveyor systems, perform mechanical calculations, and collaborate with teams to support prototype development while ensuring compliance with safety standards.

Design and implement RTL for BOOT and power-management subsystems on automotive and client SoCs. Own micro-architecture, develop RTL, drive verification, close timing, collaborate with architects, timing/VLSI/physical teams, and support silicon validation.

The Senior Digital Design Engineer will own physical implementation for IP blocks, develop floorplans, execute place-and-route, and mentor junior engineers while ensuring adherence to performance and design requirements.

The Staff Physical Design Engineer leads complex physical design for SoCs, mentors team members, and collaborates cross-functionally to ensure high-quality implementations meeting defined criteria.

The Staff Digital Design Engineer leads digital design projects, influences product direction, mentors engineers, and guides best practices across multiple technical domains.

Design high-speed D2D and SERDES products, develop analog/mixed signal IC circuit blocks, collaborate on circuit design and verification.

The role involves leading VLSI design engineering, overseeing project schedules, and developing complex test benches and verification methodologies.

The Principal Design Engineer will design high-speed analog and mixed-signal circuits, lead design reviews, and drive micro-architecture innovations for HBM PHY products.

Lead DFT ownership across projects: define test architecture, implement RTL DFT changes, perform scan insertion/LEC/CLP checks, develop test-mode timing constraints, run ATPG and timing simulations, implement/verify boundary-scan, ACJTAG, IEEE1500 and IEEE1687 (iJTAG) ICL/PDL, support post-silicon bring-up, and interact with customers and pre-sales.

Lead and execute functional verification for complex VLSI designs using SystemVerilog and UVM. Plan environments, generate test plans, develop verification environments, drive projects from concept to verification closure, and mentor teams. Prior memory IP (DDR/HBM/GDDR) verification experience is a plus.

Lead design and development of high-speed SerDes and memory interface IPs (I/Os, PLLs, clocking, datapaths). Own PCIe Gen3–6 and GDDR/DDR/LPDDR interfaces, ensure ESD, SI/PI and reliability compliance, manage cross-functional dependencies, mentor junior engineers, and communicate technical issues. Advanced process node experience preferred.

Lead design verification efforts using SystemVerilog and UVM: plan verification environments and test plans, develop functional verification environments, verify complex designs, and drive projects to verification closure. Memory IP (DDR/HBM/GDDR) experience is a plus.

The Lead Design Engineer will code in RTL, create datapath designs, and manage complex FIFO design while collaborating with analog design teams.

Design and optimize structural and thermal components for the e^pump, ensuring manufacturability while meeting safety requirements. Collaborate with teams on refining designs based on feedback and validate product performance through comprehensive testing and analysis.

Design and deliver high-speed Ethernet switching hardware from specification through production. Tasks include component selection, schematic capture, PCB stackup and layout collaboration, signal/power integrity simulation, prototype bring-up and debug, CM handoff, and driving cross-functional system-level troubleshooting and manufacturing readiness.

The role involves overseeing engineering assignments for substation projects, ensuring adherence to safety, quality, and budget requirements. Responsibilities include evaluating engineering techniques, providing technical support, collaborating with suppliers, and coordinating tasks for entry-level engineers.

The role involves translating system requirements into hardware specifications, digital design, RTL coding, and collaborating with verification and physical design teams.

The Senior SoC Logic Design Engineer will design and develop SoC solutions, oversee RTL coding and simulation, and ensure integration and quality of designs for various applications.

Design and verify analog/RF IC layouts from floorplanning through tape-out. Perform LVS/DRC/ERC/ESD checks (Calibre), address layout-dependent effects, ESD/latch-up/IR-drop/EM fixes, and collaborate with RF designers on LNAs, mixers, PAs, and general analog blocks.

Design and deliver memory layout for advanced CMOS nodes, applying process rules, floor-planning, hierarchy layout, physical verification (LVS/DRC/ERC/EM), and chip integration while managing schedules and mentoring junior engineers.

The Staff Analog Design Engineer will manage analog IP design and development for power management products, ensuring technical quality from definition to delivery, while collaborating with multiple teams on validation and performance measurement.

The Principal Analog Design Engineer leads the design and development of power management analog IP blocks, ensuring successful transfer to production and collaboration across teams.