Top Design Engineer Jobs in Bangalore

Responsible for detailed electrical engineering of ground- and roof-mounted solar projects, including system sizing, layouts, single-line diagrams, SCADA architecture, performance estimation, bills of material, as-built drawings, and plant handover documentation. Coordinates with customers, project teams, supply chain, quality, and operations to ensure accurate and timely engineering deliverables. Requires solar design expertise and proficiency with PVSYST, Helioscope, AutoCAD, Google SketchUp, and MS Office.

Designs and develops custom mechanical tooling, fixtures, layouts, drawings, and specifications for manufacturing and operational workflows. Performs engineering analyses, resolves complex mechanical challenges, establishes tooling standards, and drives continuous improvement. Leads projects from concept through implementation, defines and documents testing, reviews engineering documentation, and collaborates with suppliers, manufacturing, engineering, and leadership teams.

Designs gearbox housing, covers, brackets, deflectors, inverter boxes, fasteners, and related hybrid/e-drive components. Develops concepts and detailed designs, creates manufacturing-ready drawings, presentations, and tolerance calculations, and interprets casting simulations and CAE results. Coordinates designs with suppliers and project teams through meetings, change management, FMEA, requirements management, and interface definition. Supports prototype testing and evaluates results with test engineers.

Develops reusable analog and mixed-signal CMOS circuit blocks, including amplifiers, LDOs, bandgaps, and charge pumps. Responsibilities include circuit design, layout supervision, simulation, verification, laboratory debugging, bench characterization, post-silicon validation, DFT collaboration, documentation, and production release. Provides technical leadership in specifications, project planning, design-team coordination, and collaboration with systems, test, product, applications, and marketing teams.

Deliver microarchitecture and RTL for Graphcore silicon: integrate IP/subsystems into SoC, maintain build/config environments, run synthesis/lint/CDC/timing checks, support verification and physical design handoffs, debug integration issues, improve automation and integration flows, and produce high-quality documentation.

Designs, develops, simulates, verifies, and optimizes analog and mixed-signal circuits, including GPIO, PLLs, LDOs, and ADCs, for advanced semiconductor process nodes. Responsibilities include floor planning, parameter extraction, test planning, performance analysis, issue resolution, and power, performance, area, timing, and yield optimization. The role collaborates with architecture and layout teams to deliver robust, high-quality semiconductor IP.

Develop and document semiconductor scribe-module electrical test structures for process development and manufacturing. Collaborate with process integration, fabrication, layout, device characterization, and scribe-build teams. Create scripts and programs to organize information, improve design verification, streamline development workflows, establish standards, and identify process improvements. Participate in technical meetings and develop innovative approaches for future scribe-team applications.

Leads analog and mixed-signal design verification for complex integrated circuits, ensuring specification compliance, performance, power, and schedule targets. Develops verification strategies, reusable UVM-based environments, testbenches, models, coverage, checkers, and regression flows. Leads technical collaboration across design and validation teams, mentors engineers, manages contractors and project resources, and drives verification methodology improvements and strategic initiatives.

Design and architect high-performance analog/mixed-signal building blocks (PLLs, ADCs/DACs, RFICs). Perform pre-/post-layout simulations and sign-off (Monte Carlo, corner, noise, EM/IR/Aging). Use Cadence Virtuoso and simulators (Spectre/HSPICE), run physical verification (Calibre/IC Validator), and reliability/power checks (Voltus/RedHawk). Drive multi-node design across planar and FinFET processes and adopt automated/script-based verification (Python/SKILL/Tcl).

Designs and develops analog and mixed-signal circuit IPs in advanced process nodes. Responsibilities include circuit design, floorplanning, simulation, behavioral modeling, parameter extraction, test planning, verification, and optimization for power, performance, area, timing, leakage, and yield. Collaborates with architecture and layout teams to resolve design issues and improve circuit robustness.

Own RTL development and microarchitecture for AI-enabled RISC-V CPU IP, including vector and matrix engines. Lead design of critical CPU blocks, optimize power, performance, area, and timing, develop detailed specifications, support functional verification, and collaborate on physical design validation. The role requires expertise in high-performance CPU pipelines, execution units, memory subsystems, cache coherency, SystemVerilog or related HDL, simulation, and waveform debugging.

Designs, micro-architects, implements, and verifies digital processing blocks for CMOS image sensors. Responsibilities include ASIC development across concept, specification, design, verification, and documentation; data path and control logic design; synthesis, clock-domain, low-power, and behavioral modeling; verification debugging; and collaboration with cross-functional teams.

Develop and maintain foundry PDK components for advanced semiconductor nodes. Perform standard-cell, SRAM, custom-circuit, interconnect, and PPA technology studies. Build automation scripts and execution flows for PDK validation and analysis. Apply knowledge of CMOS device physics, GAA, FinFETs, LVS, DRC, parasitic extraction, and transistor-level SPICE models while collaborating with PDK, technology enablement, and DTCO teams.

Design and develop single- and multiport SRAM and register file compilers across advanced process technologies. Responsibilities include CMOS circuit design, simulation, timing and margin analysis, statistical yield characterization, power and signal integrity analysis, compiler tuning and sign-off, silicon failure diagnosis, and layout review. The role also requires hands-on use of schematic, layout, circuit simulation, and waveform analysis tools, with scripting and memory DFT experience preferred.

Design and develop single- and multiport SRAM and register-file memory compilers across advanced process nodes. Responsibilities include CMOS circuit design, simulation, timing and margin analysis, statistical yield characterization, power and signal-integrity analysis, compiler sign-off, silicon failure diagnosis, and layout debugging. The role also involves power-gating and split-rail architectures, memory DFT considerations, and use of circuit simulation, schematic, layout, and scripting tools.

Designs and develops high-speed single- and multiport SRAM and register-file compilers across advanced process technologies. Responsibilities include CMOS circuit design, simulation, timing and margin analysis, statistical yield characterization, power and signal-integrity analysis, compiler tuning and sign-off, silicon failure diagnosis, and supporting memory design release. The role requires hands-on schematic, layout, simulation, waveform analysis, and scripting experience.

Design and verify SoC Design-for-Test architectures, including ATPG, MBIST, LBIST, scan insertion, and analog test features. Generate and optimize test patterns, integrate DFT requirements across RTL and physical design, develop automation scripts, analyze silicon and production test data, debug root causes, and document reusable implementations. The role collaborates with design, verification, backend, and test engineering teams.

Design and own analog layouts from block level through full chip for power-management products, including charge pumps, comparators, amplifiers, bandgaps, and regulators. Responsibilities include floorplanning, matching, electromagnetic and reliability design, die-level analog/digital and power integration, package connectivity, DRC/LVS flows, methodology development, and schedule ownership. The engineer may manage and mentor junior engineers while collaborating with circuit and layout teams.

Designs and develops embedded firmware for residential gateways using C/C++, Embedded Linux, and prplOS. Owns wireless architecture for Wi-Fi 6E and Wi-Fi 7, integrates drivers and networking stacks, and optimizes system performance with perf and Valgrind. Builds Python-based automation and unit-testing frameworks, manages IPC services, TR-181 and USP device management, Docker-based microservices, SoC abstraction layers, and Git-based release pipelines.

Staff ASIC/SoC Verification Engineer responsible for planning and executing comprehensive verification, developing reusable SystemVerilog/UVM testbenches and VIP, achieving coverage closure, and debugging GLS and timing issues. The role requires ARM-based SoC and AMBA protocol expertise, power-aware verification using UPF/CPF, scripting automation, and familiarity with formal verification and AI/ML-assisted verification. Collaboration with internal teams, external customers, and VIP providers is also required.

Leads architecture, microarchitecture, RTL design, synthesis, sign-off, and silicon bring-up for complex data-center ASICs. Serves as a digital design authority, resolving EDA and cross-domain challenges while optimizing performance, power, and area. Collaborates with verification, physical design, DFT, systems, and product teams; influences PCIe, CXL, NVMe, and SAS roadmaps; and mentors engineers. Requires extensive ASIC/SoC experience, multiple tape-outs, low-power methodologies, DFT, scripting, and high-speed protocol expertise.

Leads pre-silicon verification for complex digital SoCs and subsystems, from strategy and planning through signoff. Responsibilities include architecting UVM testbenches and DV methodologies, verifying processors, AI/ML accelerators, NoC and interfaces, driving functional and code coverage closure, and applying formal, power-aware, emulation, FPGA, and system-level validation techniques. The role provides technical leadership, mentoring, cross-functional collaboration, and verification innovation across architecture, design, firmware, software, and system teams.

Leads design verification for complex SoC and subsystem products using UVM-based environments, constrained-random testing, assertions, coverage analysis, and simulation debug. Develops reusable verification components, test plans, checkers, scoreboards, and automation frameworks. Collaborates with architecture, RTL, design, and systems teams to resolve issues and achieve silicon quality goals. Verifies processors, memories, interconnects, sensors, and peripherals while mentoring junior engineers and improving verification methodologies.

Develop and execute verification strategies focused on emulation to validate complex ASIC designs. Build testbenches, run large-scale emulation tests, debug issues with designers, maintain automation and verification infrastructure, document results, and mentor junior engineers.

Leads architecture, design, validation, and technical delivery of embedded electronic hardware for safety-critical rail and transit brake systems. Owns hardware work packages from concept through production, including ECUs, power electronics, interfaces, PCB reviews, verification, debugging, qualification, and reliability analysis. Collaborates with systems, software, manufacturing, suppliers, and global engineering teams; investigates complex issues, ensures regulatory and customer compliance, mentors engineers, and drives technical standards and project milestones.