Top Design Engineer Jobs in Bangalore

The role involves executing SoC physical design implementations, ensuring high-quality designs, performing analysis, and optimizing methodologies for efficiency in a fast-paced team environment.

As a DFT Design Engineer, you will enhance test coverage and manufacturability, developing DFT architectures and working with cross-functional teams to ensure testing of silicon solutions.

The role involves physical design implementation, static timing analysis, power domain analysis, and collaborating with teams to optimize SoC designs.

Lead DFT ownership across projects: define test architecture, implement RTL DFT changes, perform scan insertion/LEC/CLP checks, develop test-mode timing constraints, run ATPG and timing simulations, implement/verify boundary-scan, ACJTAG, IEEE1500 and IEEE1687 (iJTAG) ICL/PDL, support post-silicon bring-up, and interact with customers and pre-sales.

Lead and execute functional verification for complex VLSI designs using SystemVerilog and UVM. Plan environments, generate test plans, develop verification environments, drive projects from concept to verification closure, and mentor teams. Prior memory IP (DDR/HBM/GDDR) verification experience is a plus.

Lead design verification efforts using SystemVerilog and UVM: plan verification environments and test plans, develop functional verification environments, verify complex designs, and drive projects to verification closure. Memory IP (DDR/HBM/GDDR) experience is a plus.

The Lead Design Engineer will code in RTL, create datapath designs, and manage complex FIFO design while collaborating with analog design teams.

Lead hardware engineer for product design, developing specifications, schematics, and layouts, collaborating with teams, performing validations, and transitioning to production.

Design and implement complex analog circuits for advanced DRAM products, oversee layout processes, validate designs, and mentor junior engineers. Collaborate across multiple teams to enhance product manufacturability using AI tools.

Manage a team to deliver effective engineering designs for robotic automation systems, ensuring high quality and timely solutions. Collaborate across teams, manage design plans, and support customer interaction during project execution.

The IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in FPGA's, develop analog circuits for IO applications, work with design requirements, optimize circuits, and support post-tapeout phase.

The Principal IO Mixed Signal Design Engineer will integrate and verify mixed signal blocks in high-speed IOs for FPGAs, develop custom circuits, and support post-tapeout phases.

Design and develop analog and mixed-signal circuits for embedded Flash Memory, collaborating with teams to optimize performance and reliability while mitigating risks.

Design and implement micro-architectures in RTL for memory subsystems, verify functionality, and collaborate with cross-functional teams for debugging and synthesis.

The role involves designing GPU floorplans, optimizing chip areas, solving timing/congestion issues, and collaborating with various teams to improve designs.

Join NVIDIA's 'Layout Methodology' team to enhance layout creation and market speed for SRAM and custom Analog layouts, utilizing advanced technologies.

Design and optimize structural and thermal components for the e^pump, ensuring manufacturability while meeting safety requirements. Collaborate with teams on refining designs based on feedback and validate product performance through comprehensive testing and analysis.

Lead physical design and implementation of semiconductor circuits, mentor engineers, ensure timely product delivery, and optimize design methodologies.

Lead full RTL-to-GDSII physical design for complex SoCs, develop and optimize advanced PD methodologies, ensure timing/power/area targets, perform verification and power integrity analyses, mentor engineers, and drive tool/process improvements for successful tape-outs.

Lead physical design activities for GPUs and ASICs, focusing on design implementation, troubleshooting, and process improvements. Collaborate with teams to address design challenges and improve RTL2GDS flow.

Develop and design software systems for Hybrid Cloud and deploy them in production environments, collaborating with product management.

The ASIC Design Engineer will define and architect ASIC blocks, perform micro-architecture and logic design, and collaborate on testing and physical design for high-performance networking ASICs.

The engineer is responsible for physical implementation from RTL to GDS, including design optimization, verification, and collaboration with teams. Requires 8+ years of experience.

Design and optimize sheet metal components and thermal systems for the e^pump with a focus on manufacturability and performance requirements.

The Sr. Mask Design Engineer will layout and verify analog and mixed signal circuits, using Cadence tools and collaborating with designers for optimal circuit performance.