Top Design Engineer Jobs in Bangalore

The role involves translating system requirements into hardware specifications, digital design, RTL coding, and collaborating with verification and physical design teams.

The Senior SoC Logic Design Engineer will design and develop SoC solutions, oversee RTL coding and simulation, and ensure integration and quality of designs for various applications.

Design and verify analog/RF IC layouts from floorplanning through tape-out. Perform LVS/DRC/ERC/ESD checks (Calibre), address layout-dependent effects, ESD/latch-up/IR-drop/EM fixes, and collaborate with RF designers on LNAs, mixers, PAs, and general analog blocks.

The Staff Analog Design Engineer will manage analog IP design and development for power management products, ensuring technical quality from definition to delivery, while collaborating with multiple teams on validation and performance measurement.

The Principal Analog Design Engineer leads the design and development of power management analog IP blocks, ensuring successful transfer to production and collaboration across teams.

Lead the design and development of Power Management products focusing on digital design architecture, RTL implementation, and collaboration with cross-functional teams for efficient integration.

Lead and manage a new analog design team to deliver innovative analog circuits for mixed-signal compute products, mentor teams, and provide technical guidance.

The role involves integrating memory IPs into digital subsystems, performing RTL design, executing verification plans, and collaborating with various teams.

The Staff Analog Design Engineer will design and develop analog IP blocks, focus on power management products, and collaborate with teams for validation and execution of complex designs.

The Senior Principal Digital Design Engineer will lead power management product development, collaborating on digital design architecture, RTL implementation, and post-silicon validation, while ensuring project goals are met.

The Staff Analog Design Engineer will design and develop analog IP blocks, work with layout engineers, validate product performance, and own technical outcomes of power management products.

The role involves leading the digital design of power management ICs, collaborating across teams, and ensuring successful implementation from RTL to post-silicon validation.

Lead digital design architecture and RTL implementation for power management ICs. Collaborate across teams, support validation, and improve design processes.

The Staff Digital Design Engineer will lead digital design architecture, RTL implementation, and collaborate with multidisciplinary teams to develop Power Management ICs, ensuring high quality and performance.

The MTS Analog Design Engineer will lead and mentor a team in developing power management products, ensuring technical objectives are met, and collaborating with various teams to facilitate product release and customer support.

Lead the design and verification of a digital sub-system within the Treo platform. Collaborate with teams to ensure requirements are met and IP meets ASIL standards. Perform RTL coding and scripting, drive innovation, and provide documentation.

The role involves leading digital design architecture, RTL implementation, trade-off analysis, and collaborating with global teams on ASIC development projects. Responsibilities include enhancing design methodologies and managing multiple projects within the team.

The role involves defining and implementing digital blocks, collaborating with teams, scripting for automation, and contributing to debugging and communication efforts.

Design and deliver memory layout for advanced CMOS nodes, applying process rules, floor-planning, hierarchy layout, physical verification (LVS/DRC/ERC/EM), and chip integration while managing schedules and mentoring junior engineers.

Lead SoC microarchitecture and RTL integration covering clocking, reset, interconnects, power, security, and functional safety. Own RTL signoffs (LINT/CDC/RDC), handoff checks, verification smokes, synthesis, requirements traceability (ISO26262/CMMi), IP integration reviews, BE report reviews, technical documentation, methodology adoption, and mentor engineering teams.

Design and optimize software and system solutions for scalable IP products (Neo NPU). Develop and optimize drivers and low-level firmware for embedded processors and emulation platforms, improve power/performance/area, support customers, and collaborate with cross-functional global teams. Functional safety and neural network knowledge are beneficial.

Design and simulate transistor-level analog/mixed-signal IC blocks (amplifiers, converters, power circuits), define architectures, integrate blocks into mixed-signal systems, present results to teams/customers, support layout, lab evaluation and test, mentor others, and improve design methodologies to meet power, timing and functional objectives.

Design full-custom I/O and analog mixed-signal layouts in planar and FinFET processes; drive floorplanning and power/IO planning; perform comprehensive layout verification (DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM/IR); own end-to-end deliverables, mentor juniors, and collaborate across sites to meet schedules and quality targets.

Design and deliver high-quality memory layouts for advanced FinFET processes. Manage floor-planning, schedule, and chip integration; perform physical verification (LVS/DRC/ERC/Antenna/EM); lead and train layout teams; document methodologies and adapt to new process rules and automation.

Design full-custom I/O and analog mixed-signal layouts in planar and FinFET technologies, own end-to-end deliverables, drive floorplanning and power/IO planning, perform comprehensive layout verification (DRC/LVS/ANT/ERC/DFM, extraction, EM/IR), debug layouts, and lead/train junior engineers while coordinating across sites.