Top Design Engineer Jobs in Bangalore

Leads architecture and design verification for digital blocks in ASIC-based SoC designs. Develops power, performance, and area-optimized microarchitectures; manages Lint, CDC, formal equivalence, ECO, and scripting flows; collaborates with geographically distributed teams; mentors engineers; and supports post-silicon debugging. Designs must be realized in silicon through ASIC tapeouts rather than FPGA implementations.

Leads pre-silicon verification for complex digital SoCs and subsystems, from strategy and planning through coverage closure and signoff. Responsibilities include architecting UVM testbenches, applying formal verification, validating NoC and interfaces, performing power-aware and performance verification, coordinating emulation, FPGA, firmware, and system teams, and mentoring engineers. The role also drives verification methodologies, system-level use cases, technical innovation, and cross-functional execution across global teams.

Leads digital design verification and architecture for key SoC blocks through ASIC tapeout. Develops microarchitectures optimized for power, performance, and area; applies lint, CDC, formal equivalence, ECO, and scripting flows; collaborates with geographically distributed teams; mentors engineers; and may support post-silicon debugging.

Lead the architecture, design, implementation, verification, characterization, and debugging of RF, analog, mixed-signal, and digital IC circuits integrated into SoCs. Collaborate with system and product teams on specifications and circuit trade-offs, analyze non-idealities, test designs in the lab, define production test requirements, and report design and evaluation results.

Leads microarchitecture and RTL design for DSP modules, including filters, modulators, demodulators, and custom blocks. Integrates DSP subsystems into SoC platforms and develops ASIC solutions meeting power, performance, and area targets. Performs design verification using SystemVerilog, UVM, Python, or C, along with synthesis and static timing analysis. Collaborates across disciplines to solve complex digital communications and semiconductor design challenges.

Leads architecture, microarchitecture, RTL design, and integration of high-performance packet-processing, interface, and system-control blocks in multi-CPU SoCs. Develops scalable ASIC solutions for optical and wireless communications, applies digital design and verification methodologies, translates requirements into PPA-efficient implementations, and supports block verification, synthesis, static timing analysis, and design automation.

Develop RTL designs for ASIC and FPGA implementations, contribute to architecture and microarchitecture, perform block integration and debug, and support verification, synthesis, timing analysis, and design sign-off. Collaborate across engineering teams, document interfaces, support silicon bring-up and root-cause analysis, evaluate reusable IP, and implement low-power techniques such as clock gating and power optimization.

Develop and validate analog serial transceiver ICs from specifications through production release. Design blocks including op-amps, comparators, references, bandgaps, charge pumps, high-voltage transmitters and receivers, and capless LDOs. Collaborate on layout, integration, design reviews, verification, reliability, yield, post-silicon debugging, system characterization, and productization support.

Lead end-to-end physical design for complex SoCs and digital blocks, including floorplanning, placement, CTS, routing, timing closure, STA, IR/EM, power integrity, and DRC/LVS sign-off. Develop P&R automation using Tcl, Python, Perl, and shell scripting; support ECOs and post-layout optimization; collaborate with RTL, STA, DFT, verification, and architecture teams; and mentor junior engineers.

Lead the design, implementation, verification, characterization, and debugging of RF, analog, mixed-signal, and digital IC sub-blocks within receiver, transmitter, and PLL subsystems. Analyze circuit non-idealities, evaluate system performance, document results, test designs in the lab, and define production test requirements. The role requires expertise in RF and mixed-signal circuits, SerDes, ADCs, DACs, PLLs, CMOS device physics, and FinFET layout.

Design and develop power management ICs from specifications through production, including switching converter architectures, analog circuit blocks, chip architecture, modeling, layout supervision, design reviews, post-silicon debug, system characterization, and productization support. The role collaborates with system, layout, test, operations, and applications teams while ensuring product reliability, yield, and performance.

Designs and develops analog circuits for advanced semiconductor process nodes and mixed-signal IPs. Responsibilities include circuit simulation, verification, floorplan optimization, layout review, test-plan development, and optimizing designs for power, performance, area, timing, and yield. The engineer collaborates with architecture, layout, and verification teams, tracks design issues, reports progress, and drives technical resolutions.

Designs and develops FPGA RTL logic, architectures, IP blocks, subsystems, and simulation models. Creates logic diagrams, prototypes, verification plans, and device bring-up software models. Optimizes designs for power, performance, and area while partnering with physical implementation teams. Reviews verification results, resolves RTL test failures, and supports full-chip integration.

Develops FPGA logic architecture, RTL designs, simulations, IP blocks, and subsystems using Verilog and VHDL. Defines microarchitecture, creates prototypes and software models, and optimizes designs for power, performance, and area. Partners with physical implementation and verification teams to validate features, resolve RTL test failures, and support device bring-up. Requires extensive FPGA, ASIC, or custom IC design experience and strong analytical and collaboration skills.

Design and architect high-performance VLSI/ASIC blocks for networking ASICs. Perform micro-architecture and Verilog RTL design, collaborate on verification and physical design, debug timing and functional issues, and optimize for throughput and power.

Architect and design high-performance networking ASIC blocks, including microarchitecture and Verilog RTL logic, optimized for throughput and power. Collaborate with verification teams on test plans and debug failures, and work with physical design teams on timing constraints, timing analysis, and timing fixes. The role requires strong ASIC debugging and problem-solving skills, knowledge of memory subsystems, clock synchronization, and high-speed serial interfaces, plus a BSEE or MSEE.

Design and integrate complex analog circuits (amplifiers, comparators, bandgaps, LDOs, charge pumps, oscillators, DLLs, IOs, sensors), develop custom digital blocks, perform parasitic modeling and simulation, manage layout and tape-out, collaborate cross-functionally for manufacturability, mentor junior designers, and apply agentic AI tools to improve PPA and delivery.

Design, implement, and integrate complex analog circuits and custom digital blocks for advanced DRAM/HBM products. Perform parasitic modeling, verification with industry simulators, oversee layout (floor-planning, placement, routing), and ensure manufacturability through cross-functional collaboration. Mentor junior designers and apply strong AI skills (agentic models, tools like Claude) to improve PPA and delivery.

Lead analog design efforts for high-speed PHY sub-blocks at advanced process nodes (12nm and below). Own specifications and implementation, collaborate with a skilled analog team, and leverage AI-assisted design workflows where applicable.

Designs, simulates, verifies, and tests VLSI components and ASIC architectures for computer and server systems. Develops algorithms, evaluates circuit performance, and supports prototype or production solutions while meeting quality, schedule, and cost targets. Collaborates with internal teams and outsourced development partners, communicates project status, resolves issues, and mentors less experienced engineers.

Develops and executes verification plans for FPGA PCIe IP, subsystem, and system-level designs. Builds testbenches, creates tests and coverage goals, analyzes coverage metrics, debugs failures, and drives bug closure. Collaborates with vendors on verification tools and methodologies, enhances FPGA design verification processes, and applies advanced techniques to improve quality and productivity. Requires strong communication, leadership, and problem-solving skills.

Designs and owns pad rings, IO connectivity, bump patterns, and related physical-design handoff deliverables for advanced storage and memory controller SoCs. Collaborates across architecture, implementation, packaging, foundry, verification, and product engineering teams. Supports IO validation, emulation, ASIC validation, silicon debug, and design improvements. The role requires expertise in IO planning, EDA tools, SoC interfaces, deliverable validation, and Tcl or Python automation.

Lead architecture and implementation of digital subsystems for Automotive Ethernet PHYs. Define micro-architecture, develop RTL (Verilog/SystemVerilog), drive digital front-end flows (lint, CDC/RDC, synthesis, STA), collaborate with mixed-signal and firmware teams, perform system partitioning, support bring-up/compliance testing, and ensure ISO 26262 and AEC-Q100 functional-safety compliance.

Performs functional and pre-silicon verification of GPU graphics, media, and display logic. Develops reusable verification plans, testbenches, simulation models, coverage, and assertions; executes tests, analyzes power and timing, debugs failures, and implements corrective measures. Collaborates with GPU architects, RTL developers, and physical design teams to validate complex features and improve verification infrastructure and methodology.

Own analog, power, and mixed-signal IC layout from floor planning through physical verification and tape-out readiness. Apply advanced techniques for matching, parasitic reduction, noise isolation, high-current routing, electromigration, thermal performance, and reliability. Lead DRC, LVS, ERC, PEX, and related sign-off activities; improve automation and reusable methodologies; collaborate cross-functionally; mentor engineers; and provide technical leadership for complex block and full-chip designs.