Top Design Engineer Jobs in Bangalore

Design and implement microarchitecture and RTL for mixed-signal, high-speed IPs using SystemVerilog. Optimize power, performance, and area; run lint/CDC/synthesis QA; perform power and performance analysis; review verification plans and resolve RTL issues; support SoC integration and deliver IP modules; develop automation for coverage closure and timing convergence.

Support pre-sales engineering for global Fire Detection System projects: review specs and MEP drawings, prepare BOMs and cost estimates, ensure compliance with NFPA/BS/EN/FM standards, create technical documentation and costing sheets, manage quality and delivery, escalate issues, coach team members, and provide customer reporting to ensure on-time, defect-free project delivery.

Design and architect high-performance analog/mixed-signal building blocks (PLLs, ADCs/DACs, RFICs). Perform pre-/post-layout simulations and sign-off (Monte Carlo, corner, noise, EM/IR/Aging). Use Cadence Virtuoso and simulators (Spectre/HSPICE), run physical verification (Calibre/IC Validator), and reliability/power checks (Voltus/RedHawk). Drive multi-node design across planar and FinFET processes and adopt automated/script-based verification (Python/SKILL/Tcl).

Design and modify standard equipment and system designs for weighing and rolling mill applications. Produce drawings, calculations, BOMs, and design verifications. Coordinate with manufacturing and testing, apply DFMEA, and recommend improvements to increase machine efficiency and quality while adhering to standards and safety.

Design and optimize mask layouts for analog, digital, and mixed-signal ICs. Perform DRC, LVS, and reliability checks, collaborate with designers and process teams, use EDA tools for layout and verification, work independently to deliver high-quality results, and mentor junior engineers.

Design and verify high-speed mixed-signal communication and high-performance digital circuits. Perform RTL coding, simulation, synthesis, timing closure, verification, and debugging at circuit and behavioral levels. Prepare test methods, specifications, datasheets, and demo boards. Collaborate with analog and digital teams and manage multiple tasks to deliver projects on time.

Design and develop reliable digital and analog electronics for defense/avionics products. Perform obsolescence redesign, simulations, derating analysis, schematic and PCB design, signal integrity and timing analysis, FPGA/VHDL development, board-level testing, verification to DO-160/DO-254/MIL-STD, root-cause analysis, test-plan creation, and coordinate with mechanical, systems and suppliers for product validation.

Lead the RTL implementation or verification of microprocessor cores, manage timing, area, and power goals, and collaborate with various design teams.

Lead chip-level power estimation, analysis, and signoff using Synopsys PrimePower across RTL-to-tape-out for advanced-node SoCs. Drive dynamic/static/leakage analysis, IR drop and PDN validation, UPF/CPF verification, synthesis and STA support, power signoff methodology, and collaborate with RTL, P&R, package, and EDA vendors to meet power budgets.

Design and validate advanced analog mixed-signal circuits for HBM products including amplifiers, comparators, bandgap refs, LDOs, charge pumps, oscillators, DLLs and IOs (DDR/LPDDR). Drive layout, EM/IR optimization, parasitic modeling, tape-out revisions, reliability verification, and cross-functional integration with power delivery, process, test, and product teams. Use industry simulators and AI tools to improve PPA and delivery.

Design, implement, and integrate complex analog circuits and custom digital blocks for advanced DRAM/HBM products. Perform parasitic modeling, verification with industry simulators, oversee layout (floor-planning, placement, routing), and ensure manufacturability through cross-functional collaboration. Mentor junior designers and apply strong AI skills (agentic models, tools like Claude) to improve PPA and delivery.

Design, implement and integrate complex analog circuits and custom digital blocks for advanced DRAM (HBM) products. Perform parasitic modeling, verification with industry simulators, manage layout/floorplanning, collaborate with cross-functional teams for manufacturability, mentor junior designers, and use agentic AI tools (e.g., Claude) to optimize PPA and accelerate delivery.

Lead and own analog IC product development for ultra-fast multiplexers and switches from definition through manufacturing. Design, develop, and evaluate integrated circuits and silicon, guide layout and verification, collaborate with systems, applications, validation and test teams, support customers, and hire and develop team members.

The BIM Design Engineer will create BIM models for ELV systems, conduct clash detection, and ensure compliance with building codes while collaborating with project teams.

Lead and develop complex highway design projects, ensuring safety, efficiency, compliance, and sustainability while mentoring junior engineers and managing resources.

Design, develop, verify, synthesize, and validate complex RTL for FPGA/ASIC/SoC products. Lead functional verification, timing and area optimization, debug across RTL/gate/silicon, collaborate with firmware, physical design, and verification, and support post-silicon bring-up.

Design and simulate transistor-level analog and mixed-signal IC blocks, create behavioral models, supervise physical layout, verify chip performance, support tape-out and silicon debug, collaborate with test/validation/packaging teams, and contribute to product definition and IP protection.

The role involves designing and verifying high-speed analog and mixed-signal circuits for photonic transceivers. Responsibilities include developing testbenches, executing test cases, and collaborating with multidisciplinary teams.

The Staff Design Verification Engineer leads verification strategy for complex analog and mixed-signal designs, developing environments and mentoring engineers while ensuring product quality.

The role involves executing RTL-to-GDSII flows, performing timing analysis, and verifying designs while collaborating with cross-functional teams on complex designs.

Lead physical design implementation and integration at block/subsystem/sub-chip/SoC levels including floorplanning, synthesis, placement, CTS, routing, STA, physical verification, formal equivalency, power integrity (IR-drop/EM) and tapeout readiness. Drive PD flow automation, team delivery against milestones, vendor/IP evaluations, and report progress, issues, and risks to management.

Lead physical design implementation and integration from block to full-chip level, covering floorplanning, synthesis, placement, CTS, routing, static timing, physical verification, formal equivalence, power/IR-drop and EM analysis. Drive flow development/automation, evaluate technology/IP/vendors, support tapeouts in leading-edge nodes, report status/risks, and collaborate with program teams. Occasional travel may be required.

Design and own micro-architecture and RTL for memory sub-system modules. Collaborate with architects, verification, timing, VLSI, FPGA and software teams to implement, verify, prototype, synthesize, timing-clean, and debug designs through post-silicon bring-up.

Execute RTL-to-GDS physical design including synthesis, P&R, CTS, floorplanning, STA and DFT. Verify and sign off designs (LVS/DRC/ERC, power/timing/power-integrity), troubleshoot violations, optimize power/frequency/area, and develop automation and methodology improvements while collaborating across teams.

Lead a small analog design team to architect and implement CMOS LR SERDES, D2D and common analog IP (PLL, DLL, ADCs, regulators, TX/RX, CDRs). Perform SPICE/Spectre/MATLAB-based design and verification, interface with layout/verification/application teams, manage delivery from concept to production, and lead pre-tapeout validation and lab chip bring-up/debug.